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Merge pull request #11018 from romanjoe/cy8c064-sb
PSOC6_SB: initial integration of Cypress Secure Boot target CY8CPROTO_064_SB
2 parents c74d67e + 9780c90 commit 979e1f0

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‎LICENSE.md

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@@ -54,3 +54,5 @@ The Python modules used by Mbed tools are used under the following licenses:
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- [pywin32](https://pypi.org/project/pywin32/) - PSF
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- [wmi](https://pypi.org/project/WMI/) - MIT
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- [psutil](https://pypi.org/project/psutil/) - BSD
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- [click](https://pypi.org/project/click/) - BSD-3-Clause
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- [cryptography](https://pypi.org/project/cryptography/) - BSD, Apache-2.0

‎features/storage/nvstore/mbed_lib.json

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"area_1_size": 16384,
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"area_2_address": "0x100FC000",
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"area_2_size": 16384
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},
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"CY8CPROTO_064_SB": {
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"area_1_address": "0x10048000",
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"area_1_size": 16384,
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"area_2_address": "0x1004C000",
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"area_2_size": 16384
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}
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}
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}

‎requirements.txt

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@@ -26,3 +26,5 @@ cmsis-pack-manager>=0.2.3,<0.3.0
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pywin32==224;platform_system=='Windows'
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wmi==1.4.9;platform_system=='Windows'
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psutil==5.6.2
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cryptography>=2.4.x,<2.5
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Click>=7.0,<7.1

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

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/*******************************************************************************
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* File Name: cycfg.c
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*
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* Description:
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* Wrapper function to initialize all generated code.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg.h"
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void init_cycfg_all(void)
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{
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init_cycfg_system();
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init_cycfg_clocks();
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init_cycfg_routing();
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init_cycfg_peripherals();
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init_cycfg_pins();
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

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/*******************************************************************************
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* File Name: cycfg.h
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*
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* Description:
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* Simple wrapper header containing all generated files.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_H)
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#define CYCFG_H
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#include "cycfg_notices.h"
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#include "cycfg_system.h"
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#include "cycfg_clocks.h"
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#include "cycfg_routing.h"
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#include "cycfg_peripherals.h"
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#include "cycfg_pins.h"
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void init_cycfg_all(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

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/*******************************************************************************
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* File Name: cycfg.timestamp
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*
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* Description:
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* Sentinel file for determining if generated source is up to date.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

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/*******************************************************************************
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* File Name: cycfg_clocks.c
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_clocks.h"
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void init_cycfg_clocks(void)
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{
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 35U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

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/*******************************************************************************
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* File Name: cycfg_clocks.h
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_CLOCKS_H)
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#define CYCFG_CLOCKS_H
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#include "cycfg_notices.h"
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#include "cy_sysclk.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define peri_0_div_16_0_ENABLED 1U
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#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
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#define peri_0_div_16_0_NUM 0U
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#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
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#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
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#define CYBSP_I2C_CLK_DIV_ENABLED 1U
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#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_I2C_CLK_DIV_NUM 1U
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void init_cycfg_clocks(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_CLOCKS_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

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/*******************************************************************************
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* File Name: cycfg_notices.h
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*
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* Description:
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* Contains warnings and errors that occurred while generating code for the
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* design.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_NOTICES_H)
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#define CYCFG_NOTICES_H
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#endif /* CYCFG_NOTICES_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

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/*******************************************************************************
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* File Name: cycfg_peripherals.c
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*
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_peripherals.h"
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const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config =
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{
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.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
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.slaveAddress1 = 8U,
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.slaveAddress2 = 0U,
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.subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS,
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.enableWakeFromSleep = false,
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};
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const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
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{
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.uartMode = CY_SCB_UART_STANDARD,
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.enableMutliProcessorMode = false,
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.smartCardRetryOnNack = false,
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = 12,
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.enableMsbFirst = false,
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.dataWidth = 8UL,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = 11UL,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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.receiverAddress = 0x0UL,
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.receiverAddressMask = 0x0UL,
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.acceptAddrInFifo = false,
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.enableCts = false,
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.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rtsRxFifoLevel = 0UL,
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.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rxFifoTriggerLevel = 63UL,
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.rxFifoIntEnableMask = 0UL,
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.txFifoTriggerLevel = 63UL,
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.txFifoIntEnableMask = 0UL,
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};
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const cy_stc_smif_config_t CYBSP_QSPI_config =
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{
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.mode = (uint32_t)CY_SMIF_NORMAL,
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.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
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.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
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.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
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};
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void init_cycfg_peripherals(void)
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{
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
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}

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