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targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG Expand file tree Collapse file tree 1 file changed +5
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lines changed Original file line number Diff line number Diff line change @@ -341,10 +341,11 @@ uint8_t SetSysClock_PLL_MSI(void)
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PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_USB ;
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PeriphClkInitStruct .UsbClockSelection = RCC_USBCLKSOURCE_MSI ; /* 48 MHz */
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HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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- /* Select LSE as clock source for LPUART1 */
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- PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_LPUART1 ;
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- PeriphClkInitStruct .Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE ;
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- HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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+
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+ /* Select LSE as clock source for LPUART1 */
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+ PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_LPUART1 ;
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+ PeriphClkInitStruct .Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE ;
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+ HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct );
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct .ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 );
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