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maciejbocianskimaciejbocianski
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hal-qspi test refactoring
Main idea of introduced changes is to ease adding support for new flash chips Major changes: - move implementation of all memory chip specific functions to memory config file (no weak functions) - add support for 1-2-2 write
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5 files changed

+260
-108
lines changed

5 files changed

+260
-108
lines changed

‎TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h

Lines changed: 80 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
// Command for reading status register
2323
#define QSPI_CMD_RDSR 0x05
2424
// Command for reading configuration register
25-
#define QSPI_CMD_RDCR 0x15
25+
#define QSPI_CMD_RDCR0 0x15
2626
// Command for writing status/configuration register
2727
#define QSPI_CMD_WRSR 0x01
2828
// Command for reading security register
@@ -41,7 +41,7 @@
4141
// WRSR operations max time [us] (datasheet max time + 15%)
4242
#define QSPI_WRSR_MAX_TIME 34500 // 30ms
4343
// general wait max time [us]
44-
#define QSPI_WAIT_MAX_TIME 10000 // 100ms
44+
#define QSPI_WAIT_MAX_TIME 100000 // 100ms
4545

4646

4747
// Commands for writing (page programming)
@@ -76,15 +76,16 @@
7676

7777
// erase operations max time [us] (datasheet max time + 15%)
7878
#define QSPI_ERASE_SECTOR_MAX_TIME 276000 // 240 ms
79-
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3000000 // 3s
80-
#define QSPI_ERASE_BLOCK_64_MAX_TIME 3500000 // 3.5s
79+
#define QSPI_ERASE_BLOCK_32_MAX_TIME 3450000 // 3s
80+
#define QSPI_ERASE_BLOCK_64_MAX_TIME 4025000 // 3.5s
8181

8282
// max frequency for basic rw operation
8383
#define QSPI_COMMON_MAX_FREQUENCY 32000000
8484

85-
#define QSPI_STATUS_REGISTER_SIZE 1
86-
#define QSPI_CONFIGURATION_REGISTER_SIZE 2
87-
#define QSPI_SECURITY_REGISTER_SIZE 1
85+
#define QSPI_STATUS_REG_SIZE 1
86+
#define QSPI_CONFIG_REG_0_SIZE 2
87+
#define QSPI_SECURITY_REG_SIZE 1
88+
#define QSPI_MAX_REG_SIZE 2
8889

8990
// status register
9091
#define STATUS_BIT_WIP (1 << 0) // write in progress bit
@@ -106,4 +107,76 @@
106107
#define CONFIG1_BIT_LH (1 << 1) // 0 = Ultra Low power mode, 1 = High performance mode
107108

108109

110+
// single quad enable flag for both dual and quad mode
111+
#define QUAD_ENABLE_IMPLEMENTATION() \
112+
\
113+
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
114+
\
115+
reg_data[0] = STATUS_BIT_QE; \
116+
qspi.cmd.build(QSPI_CMD_WRSR); \
117+
\
118+
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
119+
reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
120+
return QSPI_STATUS_ERROR; \
121+
} \
122+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
123+
\
124+
memset(reg_data, 0, QSPI_STATUS_REG_SIZE); \
125+
if (read_register(STATUS_REG, reg_data, \
126+
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
127+
return QSPI_STATUS_ERROR; \
128+
} \
129+
\
130+
return ((reg_data[0] & STATUS_BIT_QE) != 0 ? \
131+
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
132+
133+
134+
135+
#define QUAD_DISABLE_IMPLEMENTATION() \
136+
\
137+
uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \
138+
\
139+
reg_data[0] = 0; \
140+
qspi.cmd.build(QSPI_CMD_WRSR); \
141+
\
142+
if (qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
143+
reg_data, QSPI_STATUS_REG_SIZE, NULL, 0) != QSPI_STATUS_OK) { \
144+
return QSPI_STATUS_ERROR; \
145+
} \
146+
WAIT_FOR(WRSR_MAX_TIME, qspi); \
147+
\
148+
reg_data[0] = 0; \
149+
if (read_register(STATUS_REG, reg_data, \
150+
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
151+
return QSPI_STATUS_ERROR; \
152+
} \
153+
\
154+
return ((reg_data[0] & STATUS_BIT_QE) == 0 ? \
155+
QSPI_STATUS_OK : QSPI_STATUS_ERROR)
156+
157+
158+
159+
#define FAST_MODE_ENABLE_IMPLEMENTATION() \
160+
\
161+
qspi_status_t ret; \
162+
const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \
163+
uint8_t reg_data[reg_size]; \
164+
\
165+
if (read_register(STATUS_REG, reg_data, \
166+
QSPI_STATUS_REG_SIZE, qspi) != QSPI_STATUS_OK) { \
167+
return QSPI_STATUS_ERROR; \
168+
} \
169+
if (read_register(CONFIG_REG0, reg_data + QSPI_STATUS_REG_SIZE, \
170+
QSPI_CONFIG_REG_0_SIZE, qspi) != QSPI_STATUS_OK) { \
171+
return QSPI_STATUS_ERROR; \
172+
} \
173+
\
174+
reg_data[2] |= CONFIG1_BIT_LH; \
175+
qspi.cmd.build(QSPI_CMD_WRSR); \
176+
\
177+
return qspi_command_transfer(&qspi.handle, qspi.cmd.get(), \
178+
reg_data, reg_size, NULL, 0)
179+
180+
181+
109182
#endif // MBED_QSPI_FLASH_MX25R6435F_H

‎TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,6 @@
2121
// TODO: remove when fixed
2222
// when perform 4IO write, when memory indicates write finish (changing WIP bit in status register)
2323
// but actually write is still in progress and we have to wait a bit more before reading
24-
#define STM_DISCO_L475VG_IOT01A_WRITE_4IO_BUG_WORKAROUND
24+
#define STM_WRITE_4IO_BUG_WORKAROUND
2525

2626
#endif // MBED_QSPI_FLASH_CONFIG_H

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