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harrisonmutai-armharrisonmutai-arm
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Refactor ARM MSP2 target scatter files for bare metal support
1 parent 0f23373 commit b31ce7a

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5 files changed

+10
-15
lines changed
  • targets/TARGET_ARM_SSG/TARGET_MPS2
    • TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD
    • TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD
    • TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD
    • TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD
    • TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD

5 files changed

+10
-15
lines changed

‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58,13 +58,13 @@
5858
# endif
5959
#endif
6060

61-
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
61+
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
6262
#define VECTOR_SIZE 0x100
6363

6464
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
6565

6666
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
67-
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
67+
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
6868

6969
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7070
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@@ -73,7 +73,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7373
*(+RO)
7474
}
7575

76-
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
7776
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
7877
*(+RW +ZI)
7978
}

‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -58,13 +58,13 @@
5858
# endif
5959
#endif
6060

61-
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
61+
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
6262
#define VECTOR_SIZE 0x100
6363

6464
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
6565

6666
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
67-
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
67+
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
6868

6969
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7070
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@@ -73,7 +73,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7373
*(+RO)
7474
}
7575

76-
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
7776
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
7877
*(+RW +ZI)
7978
}

‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -59,13 +59,13 @@
5959
# endif
6060
#endif
6161

62-
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
62+
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
6363
#define VECTOR_SIZE 0x100
6464

6565
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
6666

6767
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
68-
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
68+
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
6969

7070
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7171
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@@ -74,7 +74,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7474
*(+RO)
7575
}
7676

77-
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
7877
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
7978
*(+RW +ZI)
8079
}

‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -59,13 +59,13 @@
5959
# endif
6060
#endif
6161

62-
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
62+
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
6363
#define VECTOR_SIZE 0x100
6464

6565
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
6666

6767
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
68-
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
68+
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
6969

7070
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7171
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@@ -74,7 +74,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7474
*(+RO)
7575
}
7676

77-
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
7877
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
7978
*(+RW +ZI)
8079
}

‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,13 +60,13 @@
6060
# endif
6161
#endif
6262

63-
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
63+
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
6464
#define VECTOR_SIZE 0x100
6565

6666
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
6767

6868
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
69-
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE)
69+
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
7070

7171
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7272
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@@ -75,7 +75,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
7575
*(+RO)
7676
}
7777

78-
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
7978
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
8079
*(+RW +ZI)
8180
}

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