Skip to content

Commit bf2f24f

Browse files
cmonrcmonr
authored
Merge pull request #6147 from codeauroraforum/Increase_Speed_LPC54628
LPC546XX: Add support for 220MHz core speed available on LPC54628
2 parents d44f999 + 069c80b commit bf2f24f

File tree

24 files changed

+1119
-379
lines changed

24 files changed

+1119
-379
lines changed

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c

Lines changed: 69 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,12 @@
11
/*
2+
* The Clear BSD License
23
* Copyright (c) 2015, Freescale Semiconductor, Inc.
34
* Copyright 2016-2017 NXP
5+
* All rights reserved.
46
*
57
* Redistribution and use in source and binary forms, with or without modification,
6-
* are permitted provided that the following conditions are met:
8+
* are permitted (subject to the limitations in the disclaimer below) provided
9+
* that the following conditions are met:
710
*
811
* o Redistributions of source code must retain the above copyright notice, this list
912
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
1619
* contributors may be used to endorse or promote products derived from this
1720
* software without specific prior written permission.
1821
*
22+
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
1923
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
2024
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2125
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,11 +49,11 @@
4549
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
4650
!!ClocksProfile
4751
product: Clocks v1.0
48-
processor: LPC54618J512
49-
package_id: LPC54618J512ET180
52+
processor: LPC54628J512
53+
package_id: LPC54628J512ET180
5054
mcu_data: ksdk2_0
5155
processor_version: 0.0.0
52-
board: LPCXpresso54618
56+
board: LPCXpresso54628
5357
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
5458

5559
#include "fsl_power.h"
@@ -244,5 +248,65 @@ void BOARD_BootClockPLL180M(void)
244248
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */
245249

246250
/* Set SystemCoreClock variable. */
247-
SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
251+
SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
248252
}
253+
254+
/*******************************************************************************
255+
******************** Configuration BOARD_BootClockPLL220M *********************
256+
******************************************************************************/
257+
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
258+
!!Configuration
259+
name: BOARD_BootClockPLL220M
260+
called_from_default_init: true
261+
outputs:
262+
- {id: FRO12M_clock.outFreq, value: 12 MHz}
263+
- {id: FROHF_clock.outFreq, value: 48 MHz}
264+
- {id: MAIN_clock.outFreq, value: 220 MHz}
265+
- {id: SYSPLL_clock.outFreq, value: 220 MHz}
266+
- {id: System_clock.outFreq, value: 220 MHz}
267+
settings:
268+
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
269+
- {id: SYSCON.M_MULT.scale, value: '110', locked: true}
270+
- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
271+
- {id: SYSCON.PDEC.scale, value: '2', locked: true}
272+
- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
273+
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
274+
275+
/*******************************************************************************
276+
* Variables for BOARD_BootClockPLL220M configuration
277+
******************************************************************************/
278+
/*******************************************************************************
279+
* Code for BOARD_BootClockPLL220M configuration
280+
******************************************************************************/
281+
void BOARD_BootClockPLL220M(void)
282+
{
283+
/*!< Set up the clock sources */
284+
/*!< Set up FRO */
285+
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
286+
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
287+
being below the voltage for current speed */
288+
POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
289+
CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */
290+
291+
/*!< Set up SYS PLL */
292+
const pll_setup_t pllSetup = {
293+
.pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
294+
.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
295+
.pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
296+
.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
297+
.pllRate = 220000000U,
298+
.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
299+
};
300+
CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
301+
CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
302+
303+
/*!< Set up dividers */
304+
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
305+
306+
/*!< Set up clock selectors - Attach clocks to the peripheries */
307+
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
308+
SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
309+
/* Set SystemCoreClock variable. */
310+
SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
311+
}
312+

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h

Lines changed: 32 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,12 @@
11
/*
2+
* The Clear BSD License
23
* Copyright (c) 2015, Freescale Semiconductor, Inc.
34
* Copyright 2016-2017 NXP
5+
* All rights reserved.
46
*
57
* Redistribution and use in source and binary forms, with or without modification,
6-
* are permitted provided that the following conditions are met:
8+
* are permitted (subject to the limitations in the disclaimer below) provided
9+
* that the following conditions are met:
710
*
811
* o Redistributions of source code must retain the above copyright notice, this list
912
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
1619
* contributors may be used to endorse or promote products derived from this
1720
* software without specific prior written permission.
1821
*
22+
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
1923
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
2024
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2125
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -122,7 +126,7 @@ void BOARD_BootClockFROHF96M(void);
122126
/*******************************************************************************
123127
* Definitions for BOARD_BootClockPLL180M configuration
124128
******************************************************************************/
125-
#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
129+
#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
126130

127131
/*******************************************************************************
128132
* API for BOARD_BootClockPLL180M configuration
@@ -140,5 +144,30 @@ void BOARD_BootClockPLL180M(void);
140144
#if defined(__cplusplus)
141145
}
142146
#endif /* __cplusplus*/
143-
#endif /* _CLOCK_CONFIG_H_ */
144147

148+
/*******************************************************************************
149+
******************** Configuration BOARD_BootClockPLL220M *********************
150+
******************************************************************************/
151+
/*******************************************************************************
152+
* Definitions for BOARD_BootClockPLL220M configuration
153+
******************************************************************************/
154+
#define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */
155+
156+
/*******************************************************************************
157+
* API for BOARD_BootClockPLL220M configuration
158+
******************************************************************************/
159+
#if defined(__cplusplus)
160+
extern "C" {
161+
#endif /* __cplusplus*/
162+
163+
/*!
164+
* @brief This function executes configuration of clocks.
165+
*
166+
*/
167+
void BOARD_BootClockPLL220M(void);
168+
169+
#if defined(__cplusplus)
170+
}
171+
#endif /* __cplusplus*/
172+
173+
#endif /* _CLOCK_CONFIG_H_ */

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,12 @@
4040
// called before main
4141
void mbed_sdk_init()
4242
{
43-
BOARD_BootClockFROHF48M();
43+
if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
44+
/* LPC54628 runs at a higher core speed */
45+
BOARD_BootClockPLL220M();
46+
} else {
47+
BOARD_BootClockFROHF48M();
48+
}
4449
}
4550

4651
// Change the NMI pin to an input. This allows NMI pin to

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c

Lines changed: 69 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,12 @@
11
/*
2+
* The Clear BSD License
23
* Copyright (c) 2015, Freescale Semiconductor, Inc.
34
* Copyright 2016-2017 NXP
5+
* All rights reserved.
46
*
57
* Redistribution and use in source and binary forms, with or without modification,
6-
* are permitted provided that the following conditions are met:
8+
* are permitted (subject to the limitations in the disclaimer below) provided
9+
* that the following conditions are met:
710
*
811
* o Redistributions of source code must retain the above copyright notice, this list
912
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
1619
* contributors may be used to endorse or promote products derived from this
1720
* software without specific prior written permission.
1821
*
22+
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
1923
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
2024
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2125
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,11 +49,11 @@
4549
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
4650
!!ClocksProfile
4751
product: Clocks v1.0
48-
processor: LPC54618J512
49-
package_id: LPC54618J512ET180
52+
processor: LPC54628J512
53+
package_id: LPC54628J512ET180
5054
mcu_data: ksdk2_0
5155
processor_version: 0.0.0
52-
board: LPCXpresso54618
56+
board: LPCXpresso54628
5357
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
5458

5559
#include "fsl_power.h"
@@ -244,5 +248,65 @@ void BOARD_BootClockPLL180M(void)
244248
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */
245249

246250
/* Set SystemCoreClock variable. */
247-
SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
251+
SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
248252
}
253+
254+
/*******************************************************************************
255+
******************** Configuration BOARD_BootClockPLL220M *********************
256+
******************************************************************************/
257+
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
258+
!!Configuration
259+
name: BOARD_BootClockPLL220M
260+
called_from_default_init: true
261+
outputs:
262+
- {id: FRO12M_clock.outFreq, value: 12 MHz}
263+
- {id: FROHF_clock.outFreq, value: 48 MHz}
264+
- {id: MAIN_clock.outFreq, value: 220 MHz}
265+
- {id: SYSPLL_clock.outFreq, value: 220 MHz}
266+
- {id: System_clock.outFreq, value: 220 MHz}
267+
settings:
268+
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
269+
- {id: SYSCON.M_MULT.scale, value: '110', locked: true}
270+
- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
271+
- {id: SYSCON.PDEC.scale, value: '2', locked: true}
272+
- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
273+
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
274+
275+
/*******************************************************************************
276+
* Variables for BOARD_BootClockPLL220M configuration
277+
******************************************************************************/
278+
/*******************************************************************************
279+
* Code for BOARD_BootClockPLL220M configuration
280+
******************************************************************************/
281+
void BOARD_BootClockPLL220M(void)
282+
{
283+
/*!< Set up the clock sources */
284+
/*!< Set up FRO */
285+
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
286+
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
287+
being below the voltage for current speed */
288+
POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
289+
CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */
290+
291+
/*!< Set up SYS PLL */
292+
const pll_setup_t pllSetup = {
293+
.pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
294+
.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
295+
.pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
296+
.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
297+
.pllRate = 220000000U,
298+
.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
299+
};
300+
CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
301+
CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
302+
303+
/*!< Set up dividers */
304+
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
305+
306+
/*!< Set up clock selectors - Attach clocks to the peripheries */
307+
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
308+
SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
309+
/* Set SystemCoreClock variable. */
310+
SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
311+
}
312+

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h

Lines changed: 32 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,12 @@
11
/*
2+
* The Clear BSD License
23
* Copyright (c) 2015, Freescale Semiconductor, Inc.
34
* Copyright 2016-2017 NXP
5+
* All rights reserved.
46
*
57
* Redistribution and use in source and binary forms, with or without modification,
6-
* are permitted provided that the following conditions are met:
8+
* are permitted (subject to the limitations in the disclaimer below) provided
9+
* that the following conditions are met:
710
*
811
* o Redistributions of source code must retain the above copyright notice, this list
912
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
1619
* contributors may be used to endorse or promote products derived from this
1720
* software without specific prior written permission.
1821
*
22+
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
1923
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
2024
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2125
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -122,7 +126,7 @@ void BOARD_BootClockFROHF96M(void);
122126
/*******************************************************************************
123127
* Definitions for BOARD_BootClockPLL180M configuration
124128
******************************************************************************/
125-
#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
129+
#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
126130

127131
/*******************************************************************************
128132
* API for BOARD_BootClockPLL180M configuration
@@ -140,5 +144,30 @@ void BOARD_BootClockPLL180M(void);
140144
#if defined(__cplusplus)
141145
}
142146
#endif /* __cplusplus*/
143-
#endif /* _CLOCK_CONFIG_H_ */
144147

148+
/*******************************************************************************
149+
******************** Configuration BOARD_BootClockPLL220M *********************
150+
******************************************************************************/
151+
/*******************************************************************************
152+
* Definitions for BOARD_BootClockPLL220M configuration
153+
******************************************************************************/
154+
#define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */
155+
156+
/*******************************************************************************
157+
* API for BOARD_BootClockPLL220M configuration
158+
******************************************************************************/
159+
#if defined(__cplusplus)
160+
extern "C" {
161+
#endif /* __cplusplus*/
162+
163+
/*!
164+
* @brief This function executes configuration of clocks.
165+
*
166+
*/
167+
void BOARD_BootClockPLL220M(void);
168+
169+
#if defined(__cplusplus)
170+
}
171+
#endif /* __cplusplus*/
172+
173+
#endif /* _CLOCK_CONFIG_H_ */

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,12 @@ uint32_t FLASHIAP_ReadUid(uint32_t *addr)
5656
// called before main
5757
void mbed_sdk_init()
5858
{
59-
BOARD_BootClockFROHF48M();
59+
if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
60+
/* LPC54628 runs at a higher core speed */
61+
BOARD_BootClockPLL220M();
62+
} else {
63+
BOARD_BootClockFROHF48M();
64+
}
6065
}
6166

6267
// Change the NMI pin to an input. This allows NMI pin to

0 commit comments

Comments
 (0)