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1 | 1 | /*
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2 |
| - * Copyright (c) 2018 ARM Limited |
| 2 | + * Copyright (c) 2018 Arm Limited |
3 | 3 | *
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4 | 4 | * Licensed under the Apache License Version 2.0 (the "License");
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5 | 5 | * you may not use this file except in compliance with the License.
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27 | 27 | */
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28 | 28 |
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29 | 29 | /* CMSDK Timers */
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30 |
| -#define ARM_CMSDK_TIMER0 |
31 | 30 | #define ARM_CMSDK_TIMER1
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| 31 | +#define ARM_CMSDK_DUALTIMER |
| 32 | + |
| 33 | +/* Timer Peripherals are driven by APB System Core Clocks, |
| 34 | + * defined in system_CMSDK_CM3DS.c |
| 35 | + */ |
| 36 | +#define TIMERS_INPUT_CLOCK_FREQ_HZ 25000000U |
| 37 | + |
| 38 | +/* mbed usec high-resolution ticker configuration */ |
| 39 | +#define USEC_TIMER_DEV CMSDK_TIMER1_DEV |
| 40 | + |
| 41 | +#define usec_interval_irq_handler TIMER1_IRQHandler |
| 42 | +#define USEC_INTERVAL_IRQ TIMER1_IRQn |
| 43 | + |
| 44 | +/* The us ticker uses CMSDK Timer1, that does not have HW prescaler. |
| 45 | + * The reported shift define is necessary for the software emulated |
| 46 | + * prescaler behavior, so the ticker works as if it was ticking on a |
| 47 | + * virtually slower frequency. The value 5 sets up the ticker to work |
| 48 | + * properly in the specified frequency interval. |
| 49 | + */ |
| 50 | +#define USEC_TIMER_BIT_WIDTH 32U |
| 51 | +#define USEC_REPORTED_SHIFT 5U |
| 52 | +#define USEC_REPORTED_FREQ_HZ (TIMERS_INPUT_CLOCK_FREQ_HZ >> \ |
| 53 | + USEC_REPORTED_SHIFT) |
| 54 | +#define USEC_REPORTED_BITS (USEC_TIMER_BIT_WIDTH - USEC_REPORTED_SHIFT) |
| 55 | + |
| 56 | +/* mbed low power ticker configuration */ |
| 57 | +#define LP_TIMER_DEV CMSDK_DUALTIMER_DEV |
| 58 | + |
| 59 | +#define lp_interval_irq_handler DUALTIMER_IRQHandler |
| 60 | +#define LP_INTERVAL_IRQ DUALTIMER_IRQn |
| 61 | + |
| 62 | +/* The lp ticker a CMSDK Dual Timer that is capable of prescaling |
| 63 | + * its input clock frequency by 256 at most. Having 25MHz as input |
| 64 | + * frequency requires an additional slowing factor in order for the ticker |
| 65 | + * to operate in the specified frequency interval, thus the effective |
| 66 | + * prescaler value is going to be the sum of the HW and the virtual |
| 67 | + * prescaler values. |
| 68 | + */ |
| 69 | +#define LP_TIMER_BIT_WIDTH 32U |
| 70 | +#define LP_TIMER_HW_PRESCALER 8U |
| 71 | +#define LP_REPORTED_SHIFT 1U |
| 72 | +#define LP_REPORTED_FREQ_HZ (TIMERS_INPUT_CLOCK_FREQ_HZ >> \ |
| 73 | + (LP_TIMER_HW_PRESCALER+LP_REPORTED_SHIFT)) |
| 74 | +#define LP_REPORTED_BITS (LP_TIMER_BIT_WIDTH - LP_REPORTED_SHIFT) |
| 75 | + |
| 76 | +/* RTC PL031 */ |
| 77 | +#define RTC_PL031 |
32 | 78 |
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33 | 79 | /* ARM GPIO */
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34 | 80 | #define ARM_GPIO0
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51 | 97 | #define ARM_SPI4
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52 | 98 |
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53 | 99 | /* ARM UART */
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54 |
| -#define DEFAULT_UART_BAUDRATE 9600 |
| 100 | +#define DEFAULT_UART_BAUDRATE 9600U |
55 | 101 | #define ARM_UART0
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56 | 102 | #define ARM_UART1
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57 | 103 | #define ARM_UART2
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