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stevew817adbridge
stevew817
authored and
adbridge
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Add new target EFM32PG12
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70 files changed

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‎targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg1p.s renamed to ‎targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s

Lines changed: 134 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
;/**************************************************************************//**
2-
; * @file startup_efr32mg1p.s
2+
; * @file startup_efr32mg12p.s
33
; * @brief CMSIS Core Device Startup File
4-
; * Silicon Labs EFR32MG1P Device Series
5-
; * @version 5.0.0
4+
; * Silicon Labs EFR32MG12P Device Series
5+
; * @version 5.1.2
66
; * @date 30. January 2012
77
; *
88
; * @note
@@ -82,37 +82,54 @@ __vector_table_0x1c
8282
DCD EMU_IRQHandler ; 0: EMU Interrupt
8383
DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt
8484
DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt
85-
DCD FRC_IRQHandler ; 3: FRC Interrupt
86-
DCD MODEM_IRQHandler ; 4: MODEM Interrupt
87-
DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt
88-
DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt
89-
DCD BUFC_IRQHandler ; 7: BUFC Interrupt
90-
DCD LDMA_IRQHandler ; 8: LDMA Interrupt
91-
DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt
92-
DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt
93-
DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt
94-
DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt
95-
DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt
96-
DCD ADC0_IRQHandler ; 14: ADC0 Interrupt
97-
DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt
98-
DCD I2C0_IRQHandler ; 16: I2C0 Interrupt
99-
DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt
100-
DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt
101-
DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt
102-
DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt
103-
DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt
104-
DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt
105-
DCD CMU_IRQHandler ; 23: CMU Interrupt
106-
DCD MSC_IRQHandler ; 24: MSC Interrupt
107-
DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt
108-
DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt
109-
DCD AGC_IRQHandler ; 27: AGC Interrupt
110-
DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt
111-
DCD RTCC_IRQHandler ; 29: RTCC Interrupt
112-
DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt
113-
DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt
114-
DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt
115-
DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt
85+
DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt
86+
DCD FRC_IRQHandler ; 4: FRC Interrupt
87+
DCD MODEM_IRQHandler ; 5: MODEM Interrupt
88+
DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt
89+
DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt
90+
DCD BUFC_IRQHandler ; 8: BUFC Interrupt
91+
DCD LDMA_IRQHandler ; 9: LDMA Interrupt
92+
DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt
93+
DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt
94+
DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt
95+
DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt
96+
DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt
97+
DCD ADC0_IRQHandler ; 15: ADC0 Interrupt
98+
DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt
99+
DCD I2C0_IRQHandler ; 17: I2C0 Interrupt
100+
DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt
101+
DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt
102+
DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt
103+
DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt
104+
DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt
105+
DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt
106+
DCD CMU_IRQHandler ; 24: CMU Interrupt
107+
DCD MSC_IRQHandler ; 25: MSC Interrupt
108+
DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt
109+
DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt
110+
DCD AGC_IRQHandler ; 28: AGC Interrupt
111+
DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt
112+
DCD RTCC_IRQHandler ; 30: RTCC Interrupt
113+
DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt
114+
DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt
115+
DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt
116+
DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt
117+
DCD SMU_IRQHandler ; 35: SMU Interrupt
118+
DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt
119+
DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt
120+
DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt
121+
DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt
122+
DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt
123+
DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt
124+
DCD I2C1_IRQHandler ; 42: I2C1 Interrupt
125+
DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt
126+
DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt
127+
DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt
128+
DCD CSEN_IRQHandler ; 46: CSEN Interrupt
129+
DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt
130+
DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt
131+
DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt
132+
DCD 0 ; 50: Reserved Interrupt
116133

117134
__Vectors_End
118135
__Vectors EQU __vector_table
@@ -195,6 +212,11 @@ FRC_PRI_IRQHandler
195212
WDOG0_IRQHandler
196213
B WDOG0_IRQHandler
197214

215+
PUBWEAK WDOG1_IRQHandler
216+
SECTION .text:CODE:REORDER:NOROOT(1)
217+
WDOG1_IRQHandler
218+
B WDOG1_IRQHandler
219+
198220
PUBWEAK FRC_IRQHandler
199221
SECTION .text:CODE:REORDER:NOROOT(1)
200222
FRC_IRQHandler
@@ -305,10 +327,10 @@ CMU_IRQHandler
305327
MSC_IRQHandler
306328
B MSC_IRQHandler
307329

308-
PUBWEAK CRYPTO_IRQHandler
330+
PUBWEAK CRYPTO0_IRQHandler
309331
SECTION .text:CODE:REORDER:NOROOT(1)
310-
CRYPTO_IRQHandler
311-
B CRYPTO_IRQHandler
332+
CRYPTO0_IRQHandler
333+
B CRYPTO0_IRQHandler
312334

313335
PUBWEAK LETIMER0_IRQHandler
314336
SECTION .text:CODE:REORDER:NOROOT(1)
@@ -350,5 +372,80 @@ RFSENSE_IRQHandler
350372
FPUEH_IRQHandler
351373
B FPUEH_IRQHandler
352374

375+
PUBWEAK SMU_IRQHandler
376+
SECTION .text:CODE:REORDER:NOROOT(1)
377+
SMU_IRQHandler
378+
B SMU_IRQHandler
379+
380+
PUBWEAK WTIMER0_IRQHandler
381+
SECTION .text:CODE:REORDER:NOROOT(1)
382+
WTIMER0_IRQHandler
383+
B WTIMER0_IRQHandler
384+
385+
PUBWEAK WTIMER1_IRQHandler
386+
SECTION .text:CODE:REORDER:NOROOT(1)
387+
WTIMER1_IRQHandler
388+
B WTIMER1_IRQHandler
389+
390+
PUBWEAK PCNT1_IRQHandler
391+
SECTION .text:CODE:REORDER:NOROOT(1)
392+
PCNT1_IRQHandler
393+
B PCNT1_IRQHandler
394+
395+
PUBWEAK PCNT2_IRQHandler
396+
SECTION .text:CODE:REORDER:NOROOT(1)
397+
PCNT2_IRQHandler
398+
B PCNT2_IRQHandler
399+
400+
PUBWEAK USART2_RX_IRQHandler
401+
SECTION .text:CODE:REORDER:NOROOT(1)
402+
USART2_RX_IRQHandler
403+
B USART2_RX_IRQHandler
404+
405+
PUBWEAK USART2_TX_IRQHandler
406+
SECTION .text:CODE:REORDER:NOROOT(1)
407+
USART2_TX_IRQHandler
408+
B USART2_TX_IRQHandler
409+
410+
PUBWEAK I2C1_IRQHandler
411+
SECTION .text:CODE:REORDER:NOROOT(1)
412+
I2C1_IRQHandler
413+
B I2C1_IRQHandler
414+
415+
PUBWEAK USART3_RX_IRQHandler
416+
SECTION .text:CODE:REORDER:NOROOT(1)
417+
USART3_RX_IRQHandler
418+
B USART3_RX_IRQHandler
419+
420+
PUBWEAK USART3_TX_IRQHandler
421+
SECTION .text:CODE:REORDER:NOROOT(1)
422+
USART3_TX_IRQHandler
423+
B USART3_TX_IRQHandler
424+
425+
PUBWEAK VDAC0_IRQHandler
426+
SECTION .text:CODE:REORDER:NOROOT(1)
427+
VDAC0_IRQHandler
428+
B VDAC0_IRQHandler
429+
430+
PUBWEAK CSEN_IRQHandler
431+
SECTION .text:CODE:REORDER:NOROOT(1)
432+
CSEN_IRQHandler
433+
B CSEN_IRQHandler
434+
435+
PUBWEAK LESENSE_IRQHandler
436+
SECTION .text:CODE:REORDER:NOROOT(1)
437+
LESENSE_IRQHandler
438+
B LESENSE_IRQHandler
439+
440+
PUBWEAK CRYPTO1_IRQHandler
441+
SECTION .text:CODE:REORDER:NOROOT(1)
442+
CRYPTO1_IRQHandler
443+
B CRYPTO1_IRQHandler
444+
445+
PUBWEAK TRNG0_IRQHandler
446+
SECTION .text:CODE:REORDER:NOROOT(1)
447+
TRNG0_IRQHandler
448+
B TRNG0_IRQHandler
449+
353450

354451
END

‎targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32PG12/PeripheralNames.h

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
/***************************************************************************//**
2+
* @file PeripheralNames.h
3+
*******************************************************************************
4+
* @section License
5+
* <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
6+
*******************************************************************************
7+
*
8+
* SPDX-License-Identifier: Apache-2.0
9+
*
10+
* Licensed under the Apache License, Version 2.0 (the "License"); you may
11+
* not use this file except in compliance with the License.
12+
* You may obtain a copy of the License at
13+
*
14+
* http://www.apache.org/licenses/LICENSE-2.0
15+
*
16+
* Unless required by applicable law or agreed to in writing, software
17+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
18+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
19+
* See the License for the specific language governing permissions and
20+
* limitations under the License.
21+
*
22+
******************************************************************************/
23+
#ifndef MBED_PERIPHERALNAMES_H
24+
#define MBED_PERIPHERALNAMES_H
25+
26+
#include "em_adc.h"
27+
#include "em_usart.h"
28+
#include "em_i2c.h"
29+
30+
#ifdef __cplusplus
31+
extern "C" {
32+
#endif
33+
34+
typedef enum {
35+
ADC_0 = ADC0_BASE
36+
} ADCName;
37+
38+
typedef enum {
39+
I2C_0 = I2C0_BASE,
40+
I2C_1 = I2C1_BASE,
41+
} I2CName;
42+
43+
typedef enum {
44+
PWM_CH0 = 0,
45+
PWM_CH1 = 1,
46+
PWM_CH2 = 2,
47+
PWM_CH3 = 3
48+
} PWMName;
49+
50+
typedef enum {
51+
USART_0 = USART0_BASE,
52+
USART_1 = USART1_BASE,
53+
USART_2 = USART2_BASE,
54+
USART_3 = USART3_BASE,
55+
LEUART_0 = LEUART0_BASE,
56+
} UARTName;
57+
58+
typedef enum {
59+
SPI_0 = USART0_BASE,
60+
SPI_1 = USART1_BASE,
61+
SPI_2 = USART2_BASE,
62+
SPI_3 = USART3_BASE,
63+
} SPIName;
64+
65+
#ifdef __cplusplus
66+
}
67+
#endif
68+
69+
#endif

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