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Cruz Monrreal
authored
Merge pull request #7504 from TacoGrandeTX/feature_itm_fix
Feature itm fix
2 parents db9a0e8 + 0198481 commit dd6482b

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3 files changed

+71
-40
lines changed

3 files changed

+71
-40
lines changed

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/device/system_nrf52.c

Lines changed: 33 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -62,23 +62,23 @@ void SystemInit(void)
6262
{
6363
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
6464
Specification to see which one). */
65-
#if defined (ENABLE_SWO)
65+
#if defined (ENABLE_SWO)
6666
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
6767
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
6868
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
69-
#endif
69+
#endif
7070

7171
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
7272
Specification to see which ones). */
73-
#if defined (ENABLE_TRACE)
73+
#if defined (ENABLE_TRACE)
7474
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
7575
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
7676
NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7777
NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7878
NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7979
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
8080
NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
81-
#endif
81+
#endif
8282

8383
/* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document
8484
for your device located at https://infocenter.nordicsemi.com/ */
@@ -166,16 +166,16 @@ void SystemInit(void)
166166
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
167167
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
168168
* operations are not used in your code. */
169-
#if (__FPU_USED == 1)
169+
#if (__FPU_USED == 1)
170170
SCB->CPACR |= (3UL << 20) | (3UL << 22);
171171
__DSB();
172172
__ISB();
173-
#endif
173+
#endif
174174

175175
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
176176
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
177177
normal GPIOs. */
178-
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
178+
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
179179
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
180180
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
181181
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -185,12 +185,12 @@ void SystemInit(void)
185185
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
186186
NVIC_SystemReset();
187187
}
188-
#endif
188+
#endif
189189

190190
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
191191
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
192192
reserved for PinReset and not available as normal GPIO. */
193-
#if defined (CONFIG_GPIO_AS_PINRESET)
193+
#if defined (CONFIG_GPIO_AS_PINRESET)
194194
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
195195
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
196196
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
@@ -203,7 +203,7 @@ void SystemInit(void)
203203
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
204204
NVIC_SystemReset();
205205
}
206-
#endif
206+
#endif
207207

208208
SystemCoreClockUpdate();
209209

@@ -216,6 +216,29 @@ void SystemInit(void)
216216
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
217217
// Do nothing.
218218
}
219+
220+
/**
221+
* Mbed HAL specific code section.
222+
*
223+
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
224+
*/
225+
#if defined (DEVICE_ITM)
226+
/* Enable SWO trace functionality */
227+
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
228+
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
229+
230+
/* set SWO clock speed to 4 MHz */
231+
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
232+
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
233+
234+
/* set SWO pin */
235+
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
236+
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
237+
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
238+
239+
/* set prescaler */
240+
TPI->ACPR = 0;
241+
#endif
219242
}
220243

221244

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/system_nrf52840.c

Lines changed: 35 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -59,24 +59,24 @@ void SystemInit(void)
5959
{
6060
/* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
6161
Specification to see which one). */
62-
#if defined (ENABLE_SWO)
62+
#if defined (ENABLE_SWO)
6363
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
6464
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
6565
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
66-
#endif
66+
#endif
6767

6868
/* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
6969
Specification to see which ones). */
70-
#if defined (ENABLE_TRACE)
70+
#if defined (ENABLE_TRACE)
7171
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
7272
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
7373
NRF_P0->PIN_CNF[7] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7474
NRF_P1->PIN_CNF[0] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7575
NRF_P0->PIN_CNF[12] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7676
NRF_P0->PIN_CNF[11] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
7777
NRF_P1->PIN_CNF[9] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
78-
#endif
79-
78+
#endif
79+
8080
/* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
8181
for your device located at https://infocenter.nordicsemi.com/ */
8282
if (errata_36()){
@@ -142,16 +142,16 @@ void SystemInit(void)
142142
/* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
143143
* compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
144144
* operations are not used in your code. */
145-
#if (__FPU_USED == 1)
145+
#if (__FPU_USED == 1)
146146
SCB->CPACR |= (3UL << 20) | (3UL << 22);
147147
__DSB();
148148
__ISB();
149-
#endif
149+
#endif
150150

151151
/* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
152152
two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
153153
normal GPIOs. */
154-
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
154+
#if defined (CONFIG_NFCT_PINS_AS_GPIOS)
155155
if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
156156
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
157157
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
@@ -161,12 +161,12 @@ void SystemInit(void)
161161
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
162162
NVIC_SystemReset();
163163
}
164-
#endif
164+
#endif
165165

166166
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
167167
defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
168168
reserved for PinReset and not available as normal GPIO. */
169-
#if defined (CONFIG_GPIO_AS_PINRESET)
169+
#if defined (CONFIG_GPIO_AS_PINRESET)
170170
if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
171171
((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
172172
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
@@ -179,7 +179,7 @@ void SystemInit(void)
179179
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
180180
NVIC_SystemReset();
181181
}
182-
#endif
182+
#endif
183183

184184
SystemCoreClockUpdate();
185185

@@ -192,6 +192,30 @@ void SystemInit(void)
192192
while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
193193
// Do nothing.
194194
}
195+
196+
/**
197+
* Mbed HAL specific code section.
198+
*
199+
* The ITM has to be initialized before the SoftDevice which weren't guaranteed using the normal API.
200+
*/
201+
#if defined (DEVICE_ITM)
202+
/* Enable SWO trace functionality */
203+
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
204+
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
205+
206+
/* set SWO clock speed to 4 MHz */
207+
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
208+
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
209+
210+
/* set SWO pin */
211+
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
212+
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
213+
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
214+
215+
/* set prescaler */
216+
TPI->ACPR = 0;
217+
#endif
218+
195219
}
196220

197221

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/itm_api.c

Lines changed: 3 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -18,27 +18,11 @@
1818

1919
#include "hal/itm_api.h"
2020

21-
#include "nrf.h"
22-
#include "nrf5x_lf_clk_helper.h"
23-
24-
/* SWO frequency: 4000 kHz */
2521
void itm_init(void)
2622
{
27-
/* Enable SWO trace functionality */
28-
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
29-
NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
30-
31-
/* set SWO clock speed to 4 MHz */
32-
NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
33-
(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
34-
35-
/* set SWO pin */
36-
NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
37-
(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
38-
(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
39-
40-
/* set prescaler */
41-
TPI->ACPR = 0;
23+
/**
24+
* Initialization moved to system_nrf52840.c due to SoftDevice incompatibility.
25+
*/
4226
}
4327

4428
#endif

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