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Cruz Monrreal
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Merge pull request #8454 from ashok-rao/br-BL654-new
Adding Laird BL654 as a new MTB target
2 parents 3d859ca + bee4429 commit e942582

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/*
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* Copyright (c) 2016 Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
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* integrated circuit in a product or a software update for such product, must reproduce
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* the above copyright notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
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* used to endorse or promote products derived from this software without specific prior
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* written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary or object form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef MBED_PINNAMES_H
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#define MBED_PINNAMES_H
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#include "cmsis.h"
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#include "nrf_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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PIN_INPUT,
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PIN_OUTPUT
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} PinDirection;
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#define PORT_SHIFT 3
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///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y)
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#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num)
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typedef enum {
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PinDef(0 , 0), // P0_0 = 0...
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PinDef(0 , 1),
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PinDef(0 , 2),
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PinDef(0 , 3),
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PinDef(0 , 4),
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PinDef(0 , 5),
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PinDef(0 , 6),
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PinDef(0 , 7),
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PinDef(0 , 8),
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PinDef(0 , 9),
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PinDef(0 , 10),
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PinDef(0 , 11),
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PinDef(0 , 12),
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PinDef(0 , 13),
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PinDef(0 , 14),
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PinDef(0 , 15),
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PinDef(0 , 16),
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PinDef(0 , 17),
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PinDef(0 , 18),
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PinDef(0 , 19),
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PinDef(0 , 20),
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PinDef(0 , 21),
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PinDef(0 , 22),
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PinDef(0 , 23),
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PinDef(0 , 24),
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PinDef(0 , 25),
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PinDef(0 , 26),
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PinDef(0 , 27),
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PinDef(0 , 28),
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PinDef(0 , 29),
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PinDef(0 , 30),
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PinDef(0 , 31),
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PinDef(1 , 0), //P1_1 = 32...
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PinDef(1 , 1),
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PinDef(1 , 2),
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PinDef(1 , 3),
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PinDef(1 , 4),
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PinDef(1 , 5),
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PinDef(1 , 6),
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PinDef(1 , 7),
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PinDef(1 , 8),
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PinDef(1 , 9),
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PinDef(1 , 10),
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PinDef(1 , 11),
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PinDef(1 , 12),
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PinDef(1 , 13),
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PinDef(1 , 14),
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PinDef(1 , 15),
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// Port0
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p0 = P0_0,
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p1 = P0_1,
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p2 = P0_2,
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p3 = P0_3,
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p4 = P0_4,
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p5 = P0_5,
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p6 = P0_6,
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p7 = P0_7,
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p8 = P0_8,
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p9 = P0_9,
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p10 = P0_10,
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p11 = P0_11,
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p12 = P0_12,
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p13 = P0_13,
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p14 = P0_14,
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p15 = P0_15,
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p16 = P0_16,
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p17 = P0_17,
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p18 = P0_18,
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p19 = P0_19,
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p20 = P0_20,
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p21 = P0_21,
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p22 = P0_22,
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p23 = P0_23,
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p24 = P0_24,
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p25 = P0_25,
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p26 = P0_26,
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p27 = P0_27,
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p28 = P0_28,
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p29 = P0_29,
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p30 = P0_30,
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p31 = P0_31,
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// Port1
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p32 = P1_0,
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p33 = P1_1,
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p34 = P1_2,
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p35 = P1_3,
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p36 = P1_4,
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p37 = P1_5,
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p38 = P1_6,
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p39 = P1_7,
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p40 = P1_8,
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p41 = P1_9,
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p42 = P1_10,
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p43 = P1_11,
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p44 = P1_12,
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p45 = P1_13,
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p46 = P1_14,
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p47 = P1_15,
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// Not connected
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NC = (int)0xFFFFFFFF,
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SIO_0 = P0_0,
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SIO_1 = P0_1,
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SIO_2 = P0_2,
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SIO_3 = P0_3,
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SIO_4 = P0_4,
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SIO_5 = P0_5,
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SIO_6 = P0_6,
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SIO_7 = P0_7,
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SIO_8 = P0_8,
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SIO_9 = P0_9, //NFC1
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SIO_10 = P0_10, //NFC2
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SIO_11 = P0_11,
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SIO_12 = P0_12,
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SIO_13 = P0_13,
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SIO_14 = P0_14,
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SIO_15 = P0_15,
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SIO_16 = P0_16,
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SIO_17 = P0_17,
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SIO_18 = NC,
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SIO_19 = P0_19,
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SIO_20 = P0_20,
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SIO_21 = P0_21,
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SIO_22 = P0_22,
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SIO_23 = P0_23,
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SIO_24 = P0_24,
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SIO_25 = P0_25,
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SIO_26 = P0_26,
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SIO_27 = P0_27,
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SIO_28 = P0_28,
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SIO_29 = P0_29,
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SIO_30 = P0_30,
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SIO_31 = P0_31,
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SIO_32 = P1_0,
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SIO_33 = P1_1,
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SIO_34 = P1_2,
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SIO_35 = P1_3,
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SIO_36 = P1_4,
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SIO_37 = P1_5,
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SIO_38 = P1_6,
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SIO_39 = P1_7,
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SIO_40 = P1_8,
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SIO_41 = P1_9,
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SIO_42 = P1_10,
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SIO_43 = P1_11,
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SIO_44 = P1_12,
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SIO_45 = P1_13,
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SIO_46 = P1_14,
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SIO_47 = P1_15,
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LED1 = SIO_38,
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LED2 = SIO_39,
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LED3 = SIO_37,
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LED_RED = LED1,
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LED_GREEN = LED3,
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LED_BLUE = LED2,
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BUTTON1 = SIO_33,
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USER_BUTTON = BUTTON1,
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//Nordic SDK pin names
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RX_PIN_NUMBER = SIO_8,
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TX_PIN_NUMBER = SIO_6,
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CTS_PIN_NUMBER = SIO_7,
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RTS_PIN_NUMBER = SIO_5,
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// mBed interface Pins
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USBTX = TX_PIN_NUMBER,
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USBRX = RX_PIN_NUMBER,
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STDIO_UART_TX = TX_PIN_NUMBER,
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STDIO_UART_RX = RX_PIN_NUMBER,
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STDIO_UART_CTS = CTS_PIN_NUMBER,
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STDIO_UART_RTS = RTS_PIN_NUMBER,
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SPI_PSELMOSI0 = SIO_45,
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SPI_PSELMISO0 = SIO_46,
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SPI_PSELSS0 = SIO_42, //CS for SD card on MTB
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SPI_PSELSCK0 = SIO_47,
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SPI_PSELMOSI1 = SIO_30,
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SPI_PSELMISO1 = SIO_29,
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SPI_PSELSS1 = SIO_41, //CS for LCD on MTB
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SPI_PSELSCK1 = SIO_44,
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//Default SPI
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SPI_MOSI = SPI_PSELMOSI0,
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SPI_MISO = SPI_PSELMISO0,
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SPI_SCK = SPI_PSELSCK0,
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SPI_CS = SPI_PSELSS0,
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/*
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SPIS_PSELMOSI = P1_2,
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SPIS_PSELMISO = P1_3,
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SPIS_PSELSS = P1_1,
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SPIS_PSELSCK = P1_4,
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*/
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I2C_SDA0 = SIO_26,
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I2C_SCL0 = SIO_27,
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I2C_SDA1 = SIO_25,
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I2C_SCL1 = SIO_28,
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//Default I2C
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I2C_SCL = I2C_SCL0,
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I2C_SDA = I2C_SDA0,
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UART_TX1 = SIO_16,
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UART_RX1 = SIO_15,
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UART_TX2 = SIO_21,
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UART_RX2 = SIO_24,
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//Default UART
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UART_TX = UART_TX1,
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UART_RX = UART_RX1,
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/* QSPI */
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QSPI1_IO0 = P0_20,
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QSPI1_IO1 = P0_21,
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QSPI1_IO2 = P0_22,
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QSPI1_IO3 = P0_23,
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QSPI1_SCK = P0_19,
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QSPI1_CSN = P0_17,
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/* QSPI FLASH */
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QSPI_FLASH1_IO0 = QSPI1_IO0,
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QSPI_FLASH1_IO1 = QSPI1_IO1,
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QSPI_FLASH1_IO2 = QSPI1_IO2,
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QSPI_FLASH1_IO3 = QSPI1_IO3,
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QSPI_FLASH1_SCK = QSPI1_SCK,
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QSPI_FLASH1_CSN = QSPI1_CSN,
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//MTB aliases
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GP0 = SIO_33,
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GP1 = SIO_34,
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AIN0 = SIO_2,
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AIN1 = SIO_3,
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AIN2 = SIO_4,
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GP2 = SIO_42,
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GP3 = SIO_43,
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GP4 = SIO_19,
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GP5 = SIO_17, //A0 for LCD on MTB
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GP6 = SIO_40, //RESET for LCD on MTB
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GP7 = SIO_41,
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GP8 = SIO_12,
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} PinName;
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typedef enum {
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PullNone = 0,
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PullDown = 1,
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PullUp = 3,
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PullDefault = PullUp
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} PinMode;
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#ifdef __cplusplus
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}
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#endif
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#endif
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
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// Check the 'features' section of the target description in 'targets.json' for more details.
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_DEVICE_H
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#define MBED_DEVICE_H
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#include "objects.h"
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#endif

targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/mbed_lib.json

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"NRF52_ERRATA_20"
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],
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"target.console-uart-flow-control": "RTSCTS"
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},
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"MTB_LAIRD_BL654": {
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"target.macros_add": [
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"CONFIG_GPIO_AS_PINRESET",
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"NRF52_ERRATA_20"
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],
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"target.lf_clock_src": "NRF_LF_SRC_RC",
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"target.console-uart-flow-control": null
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}
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}
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}

targets/targets.json

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"release_versions": ["5"],
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"device_name": "nRF52840_xxAA"
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},
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"MTB_LAIRD_BL654": {
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"inherits": ["MCU_NRF52840"],
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"release_versions": ["5"],
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"device_name": "nRF52840_xxAA",
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"detect_code": ["0465"],
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"features_remove": ["CRYPTOCELL310"],
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"macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"],
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"overrides": {
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"lf_clock_src": "NRF_LF_SRC_RC"
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}
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},
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"BLUEPILL_F103C8": {
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"inherits": ["FAMILY_STM32"],
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"core": "Cortex-M3",

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