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Merge pull request #2531 from radhika-raghavendran/master
ncs36510 from ON Semiconductor
2 parents eeead56 + 2dc3806 commit ea56684

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‎hal/targets.json

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"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
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"features": ["IPV4"],
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"release_versions": ["2", "5"]
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},
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"NCS36510": {
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"inherits": ["Target"],
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"core": "Cortex-M3",
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"extra_labels": ["ONSEMI"],
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"post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
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"macros": ["REVD", "CM3", "CPU_NCS36510", "TARGET_NCS36510"],
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"progen": {"target": "ncs36510"},
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"progen_target": "ncs36510",
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"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
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"device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
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"release_versions": ["2", "5"]
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}
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}

‎hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h

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/**************************************************************************/
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/**
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* @file ARMCM3.h
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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* for CM3 Device Series
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* @version V1.05
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* @date 26. July 2011
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*
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* @note
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* Copyright (C) 2010-2011 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef ARMCM3_H
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#define ARMCM3_H
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/**
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** ARMCM3 specific Interrupt Numbers ********************************************************/
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Tim0_IRQn = 0,
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Tim1_IRQn = 1,
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Tim2_IRQn = 2,
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Uart1_IRQn = 3,
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Spi_IRQn = 4,
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I2C_IRQn = 5,
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Gpio_IRQn = 6,
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Rtc_IRQn = 7,
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Flash_IRQn = 8,
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MacHw_IRQn = 9,
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Aes_IRQn = 10,
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Adc_IRQn = 11,
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ClockCal_IRQn = 12,
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Uart2_IRQn = 13,
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Uvi_IRQn = 14,
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Dma_IRQn = 15,
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DbgPwrUp_IRQn = 16,
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Spi2_IRQn = 17,
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I2C2_IRQn = 18,
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FVDDHComp_IRQn = 19
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} IRQn_Type;
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/**
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/** Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
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//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
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//#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
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//#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
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//#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
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#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
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#include "system_NCS36510.h" /* System Header */
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#endif /* ARMCM3_H */

‎hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/TOOLCHAIN_ARM/NCS36510.sct

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#! armcc -E
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#define Heap_Size 0x0400
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LR_IROM1 0x00003000 0x0004F000 { ; load region size_region
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ER_IROM1 0x00003000 0x0004F000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (*)
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}
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; no uvisor support at this time
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;ARM_LIB_STACK AlignExpr(+0, 8) EMPTY 0x1000 {}
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ARM_LIB_STACK 0x3FFF4000 EMPTY 0x1000 {}
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RW_IRAM0 +0 {
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.ANY(+RW +ZI)
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}
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RW_IRAM1 ImageLimit(RW_IRAM0) EMPTY Heap_Size { ; Heap region growing up
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}
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ARM_LIB_HEAP AlignExpr(+0, 8) ALIGN 8 EMPTY (0x3FFF4000 + 0xC000 - AlignExpr(ImageLimit(RW_IRAM1),8) ) {}
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}

‎hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/TOOLCHAIN_ARM/startup_NCS36510.s

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;/* File: startup_ncs36510.s
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; * Purpose: startup file for Cortex-M3 devices. Should use with
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; * ARMGCC for ARM Embedded Processors
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; * Version: V2.00
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; * Date: 25 Feb 2016
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; *
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; */
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;/* Copyright (c) 2011 - 2014 ARM LIMITED
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;
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; All rights reserved.
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; - Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; - Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; - Neither the name of ARM nor the names of its contributors may be used
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; to endorse or promote products derived from this software without
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; specific prior written permission.
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; *
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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; ---------------------------------------------------------------------------*/
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0x3000 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
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__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD fIrqTim0Handler
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DCD fIrqTim1Handler
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DCD fIrqTim2Handler
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DCD fIrqUart1Handler
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DCD fIrqSpiHandler
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DCD fIrqI2CHandler
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DCD fIrqGpioHandler
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DCD fIrqRtcHandler
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DCD fIrqFlashHandler
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DCD fIrqMacHwHandler
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DCD fIrqAesHandler
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DCD fIrqAdcHandler
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DCD fIrqClockCalHandler
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DCD fIrqUart2Handler
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DCD fIrqUviHandler
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DCD fIrqDmaHandler
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DCD fIrqDbgPwrUpHandler
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DCD fIrqSpi2Handler
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DCD fIrqI2C2Handler
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DCD fIrqFVDDHCompHandler
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT fIrqTim0Handler [WEAK]
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EXPORT fIrqTim1Handler [WEAK]
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EXPORT fIrqTim2Handler [WEAK]
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EXPORT fIrqUart1Handler [WEAK]
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EXPORT fIrqSpiHandler [WEAK]
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EXPORT fIrqI2CHandler [WEAK]
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EXPORT fIrqGpioHandler [WEAK]
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EXPORT fIrqRtcHandler [WEAK]
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EXPORT fIrqFlashHandler [WEAK]
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EXPORT fIrqMacHwHandler [WEAK]
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EXPORT fIrqAesHandler [WEAK]
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EXPORT fIrqAdcHandler [WEAK]
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EXPORT fIrqClockCalHandler [WEAK]
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EXPORT fIrqUart2Handler [WEAK]
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EXPORT fIrqUviHandler [WEAK]
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EXPORT fIrqDmaHandler [WEAK]
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EXPORT fIrqDbgPwrUpHandler [WEAK]
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EXPORT fIrqSpi2Handler [WEAK]
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EXPORT fIrqI2C2Handler [WEAK]
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EXPORT fIrqFVDDHCompHandler [WEAK]
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fIrqTim0Handler
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fIrqTim1Handler
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fIrqTim2Handler
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fIrqUart1Handler
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fIrqSpiHandler
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fIrqI2CHandler
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fIrqGpioHandler
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fIrqRtcHandler
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fIrqFlashHandler
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fIrqMacHwHandler
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fIrqAesHandler
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fIrqAdcHandler
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fIrqClockCalHandler
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fIrqUart2Handler
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fIrqUviHandler
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fIrqDmaHandler
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fIrqDbgPwrUpHandler
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fIrqSpi2Handler
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fIrqI2C2Handler
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fIrqFVDDHCompHandler
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DefaultISR
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B .
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ENDP
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EXPORT __user_initial_stackheap
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IMPORT |Image$$ARM_LIB_HEAP$$Base|
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IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit|
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__user_initial_stackheap PROC
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LDR R0, = |Image$$ARM_LIB_HEAP$$Base|
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LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit|
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BX LR
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ENDP
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ALIGN
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END

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