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jeromecoutant0xc0170
jeromecoutant
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0xc0170
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NUCLEO_WB55RG: HAL API updates to get SLEEP, RTC and LPTICKER OK
- astyle OK - file alignment with other families - HSE, MSI, HSI clock support - LPTICKER with RTC and LPTIM tested
1 parent f07d570 commit f913a31

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13 files changed

+576
-467
lines changed

13 files changed

+576
-467
lines changed

‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/PinNames.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ typedef enum {
3939
PA_5 = 0x05,
4040
PA_6 = 0x06,
4141
PA_7 = 0x07,
42-
PA_7_ALT0 = PA_7|ALT0,
42+
PA_7_ALT0 = PA_7 | ALT0,
4343
PA_8 = 0x08,
4444
PA_9 = 0x09,
4545
PA_10 = 0x0A,
@@ -59,7 +59,7 @@ typedef enum {
5959
PB_7 = 0x17,
6060
PB_8 = 0x18,
6161
PB_9 = 0x19,
62-
PB_9_ALT0 = PB_9|ALT0,
62+
PB_9_ALT0 = PB_9 | ALT0,
6363
PB_10 = 0x1A,
6464
PB_11 = 0x1B,
6565
PB_12 = 0x1C,

‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/system_clock.c

Lines changed: 109 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -13,18 +13,35 @@
1313
* See the License for the specific language governing permissions and
1414
* limitations under the License.
1515
*/
16+
17+
/**
18+
* This file configures the system clock as follows:
19+
*-----------------------------------------------------------------------------
20+
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
21+
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
22+
* | 3- USE_PLL_HSI (internal 16 MHz)
23+
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
24+
*-----------------------------------------------------------------------------
25+
* SYSCLK(MHz) | 64
26+
* AHBCLK (MHz) | 64
27+
* APB1CLK (MHz) | 64
28+
* APB2CLK (MHz) | 64
29+
* USB capable | NO // todo
30+
*-----------------------------------------------------------------------------
31+
**/
32+
1633
#include "stm32wbxx.h"
17-
#include "mbed_assert.h"
34+
#include "mbed_error.h"
1835

1936
// Clock source is selected with CLOCK_SOURCE in json config
2037
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (not available)
2138
#define USE_PLL_HSE_XTAL 0x4 // Use external 32 MHz xtal (X1 on board + need HW patch)
2239
#define USE_PLL_HSI 0x2 // Use HSI 16MHz internal clock
23-
#define USE_PLL_MSI 0x1 // Use MSI 4MHz internal clock (default)
40+
#define USE_PLL_MSI 0x1 // Use MSI internal clock
2441

2542
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
2643

27-
#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
44+
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
2845
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
2946
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
3047

@@ -45,6 +62,7 @@ void Configure_RF_Clock_Sources(void);
4562
* @param None
4663
* @retval None
4764
*/
65+
4866
void SetSysClock(void)
4967
{
5068
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
@@ -59,16 +77,16 @@ void SetSysClock(void)
5977
{
6078
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
6179
/* 3- If fail start with HSI clock */
62-
if (SetSysClock_PLL_HSI()==0)
80+
if (SetSysClock_PLL_HSI() == 0)
6381
#endif
6482
{
6583
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
6684
/* 4- If fail start with MSI clock */
6785
if (SetSysClock_PLL_MSI() == 0)
6886
#endif
6987
{
70-
while(1) {
71-
MBED_ASSERT(1);
88+
{
89+
error("SetSysClock failed\n");
7290
}
7391
}
7492
}
@@ -89,24 +107,41 @@ void SetSysClock(void)
89107
/******************************************************************************/
90108
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
91109
{
92-
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
110+
// System is fully clocked @ 32MHz from HSE
111+
//return 1;
112+
93113
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
114+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
94115

116+
#if MBED_CONF_TARGET_LSE_AVAILABLE
117+
// Enable LSE Oscillator to automatically calibrate the MSI clock
118+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
119+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
120+
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
121+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
122+
return 0; // FAIL
123+
}
124+
125+
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
126+
HAL_RCCEx_DisableLSECSS();
127+
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
128+
129+
130+
// HSE has been turned on during system init
95131
// Enable HSE oscillator and activate PLL with HSE as source
96-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
132+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
97133
if (bypass == 0) {
98-
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 32 MHz xtal on OSC_IN/OSC_OUT
134+
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
99135
} else {
100-
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 32 MHz clock on OSC_IN
136+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 32 MHz clock on OSC_IN
101137
}
102-
103-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
104-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
105-
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
106-
RCC_OscInitStruct.PLL.PLLN = 16;
107-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
108-
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
109-
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4;
138+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 32 MHz
139+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
140+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV8; // 4 MHz
141+
RCC_OscInitStruct.PLL.PLLN = 32; // 128 MHz
142+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; // 64 MHz // RCC_SYSCLKSOURCE_PLLCLK
143+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5;
144+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
110145

111146
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
112147
return 0; // FAIL
@@ -125,12 +160,19 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
125160
return 0; // FAIL
126161
}
127162

163+
// Disable MSI Oscillator
164+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
165+
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
166+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
167+
HAL_RCC_OscConfig(&RCC_OscInitStruct);
168+
128169
// Output clock on MCO1 pin(PA8) for debugging purpose
129170
#if DEBUG_MCO == 2
130-
if (bypass == 0)
131-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // xx MHz
132-
else
133-
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz
171+
if (bypass == 0) {
172+
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_4); // 8 MHz
173+
} else {
174+
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
175+
}
134176
#endif
135177

136178
return 1;
@@ -152,12 +194,12 @@ uint8_t SetSysClock_PLL_HSI(void)
152194
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
153195
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
154196
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
155-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
156-
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
157-
RCC_OscInitStruct.PLL.PLLN = 16;
197+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
198+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; // 8 MHz
199+
RCC_OscInitStruct.PLL.PLLN = 16; // 128 MHz
158200
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
159201
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
160-
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
202+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; // 64 MHz // RCC_SYSCLKSOURCE_PLLCLK
161203

162204
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
163205
return 0; // FAIL
@@ -171,7 +213,7 @@ uint8_t SetSysClock_PLL_HSI(void)
171213
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; // 64 MHz
172214
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 64 MHz
173215
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
174-
216+
175217
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
176218
return 0; // FAIL
177219
}
@@ -193,24 +235,47 @@ uint8_t SetSysClock_PLL_MSI(void)
193235
{
194236
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
195237
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
238+
// RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; // USB todo
239+
240+
#if MBED_CONF_TARGET_LSE_AVAILABLE
241+
// Enable LSE Oscillator to automatically calibrate the MSI clock
242+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
243+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
244+
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
245+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
246+
return 0; // FAIL
247+
}
248+
249+
/* Enable the CSS interrupt in case LSE signal is corrupted or not present */
250+
HAL_RCCEx_DisableLSECSS();
251+
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
196252

197253
// Enable MSI Oscillator and activate PLL with MSI as source
198254
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
199255
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
200256
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
201-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
257+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; // 4 MHz
202258
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
203259
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
204-
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
205-
RCC_OscInitStruct.PLL.PLLN = 32;
206-
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
260+
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; // 4 MHz
261+
RCC_OscInitStruct.PLL.PLLN = 32; // 128 MHz
262+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; // 64 MHz // RCC_SYSCLKSOURCE_PLLCLK
207263
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5;
208264
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
209-
210265
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
211266
return 0; // FAIL
212267
}
213268

269+
#if MBED_CONF_TARGET_LSE_AVAILABLE
270+
/* Enable MSI Auto-calibration through LSE */
271+
HAL_RCCEx_EnableMSIPLLMode();
272+
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
273+
274+
/* Select MSI output as USB clock source */
275+
// PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
276+
// PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
277+
// HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
278+
214279
// Select PLL as system clock source and configure the clocks dividers
215280
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
216281
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
@@ -224,13 +289,6 @@ uint8_t SetSysClock_PLL_MSI(void)
224289
return 0; // FAIL
225290
}
226291

227-
// Calibrate MSI
228-
LL_PWR_EnableBkUpAccess();
229-
LL_RCC_ForceBackupDomainReset();
230-
LL_RCC_ReleaseBackupDomainReset();
231-
LL_RCC_LSE_Enable();
232-
while (LL_RCC_LSE_IsReady() != 1) {}
233-
LL_RCC_MSI_EnablePLLMode();
234292

235293
// Output clock on MCO1 pin(PA8) for debugging purpose
236294
#if DEBUG_MCO == 4
@@ -243,11 +301,21 @@ uint8_t SetSysClock_PLL_MSI(void)
243301

244302
void Configure_RF_Clock_Sources(void)
245303
{
304+
// Reset backup domain
305+
if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
306+
// Write twice the value to flush the APB-AHB bridge
307+
// This bit shall be written in the register before writing the next one
308+
HAL_PWR_EnableBkUpAccess();
309+
HAL_PWR_EnableBkUpAccess();
310+
__HAL_RCC_BACKUPRESET_FORCE();
311+
__HAL_RCC_BACKUPRESET_RELEASE();
312+
}
313+
246314
/**
247315
* Select LSE clock
248316
*/
249317
LL_RCC_LSE_Enable();
250-
while(!LL_RCC_LSE_IsReady());
318+
while (!LL_RCC_LSE_IsReady());
251319

252320
/**
253321
* Select wakeup source of BLE RF
@@ -263,7 +331,7 @@ void Configure_RF_Clock_Sources(void)
263331
* Set RNG on HSI48
264332
*/
265333
LL_RCC_HSI48_Enable();
266-
while(!LL_RCC_HSI48_IsReady());
334+
while (!LL_RCC_HSI48_IsReady());
267335
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
268336

269337
return;

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