Merge pull request #1626 from mtkrtk/rz_a1h_async_patch

[Renesas RZ/A1H] Enable asynchronous communications

Author: 0xc0170

libraries/mbed/api/CThunk.h

@@ -24,7 +24,7 @@
 
 #define CTHUNK_ADDRESS 1
 
-#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)
+#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)) && ! defined(__CORTEX_A9)
 #define CTHUNK_VARIABLES volatile uint32_t code[1]
 /**
 * CTHUNK disassembly for Cortex-M3/M4 (thumb2):
@@ -38,7 +38,7 @@
 */
 #define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
 
-#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)
+#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_A9)
 /*
 * CTHUNK disassembly for Cortex M0 (thumb):
 * * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
@@ -194,6 +194,24 @@ class CThunk
             m_thunk.callback = (uint32_t)&m_callback;
             m_thunk.trampoline = (uint32_t)&trampoline;
 
+#if defined(__CORTEX_A9)
+            /* Data cache clean */
+            /* Cache control */
+            {
+                uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0;
+                uint32_t end_addr   = (uint32_t)&m_thunk + sizeof(m_thunk);
+                uint32_t addr;
+                
+                /* Data cache clean and invalid */
+                for (addr = start_addr; addr < end_addr; addr += 0x20) {
+                    __v7_clean_inv_dcache_mva((void *)addr);
+                }
+                /* Instruction cache invalid */
+                __v7_inv_icache_all();
+                __ca9u_inv_tlb_all();
+                __v7_inv_btac();
+            }
+#endif
             __ISB();
             __DSB();
         }

libraries/mbed/common/SPI.cpp

@@ -124,7 +124,12 @@ int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, i
     if (_transaction_buffer.full()) {
         return -1; // the buffer is full
     } else {
+        __disable_irq();
         _transaction_buffer.push(transaction);
+        if (!spi_active(&_spi)) {
+            dequeue_transaction();
+        }
+        __enable_irq();
         return 0;
     }
 #else

libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h

@@ -754,11 +754,12 @@ typedef enum IRQn
                                    region.outer_norm_t = WB_WA; \
                                    region.mem_t = NORMAL; \
                                    region.sec_t = NON_SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
+                                   region.xn_t = EXECUTE; \
                                    region.priv_t = RW; \
                                    region.user_t = RW; \
                                    region.sh_t = NON_SHARED; \
                                    __get_section_descriptor(&descriptor_l1, region);
+
 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
                                    region.domain = 0x0; \
@@ -788,7 +789,7 @@ typedef enum IRQn
                                    region.user_t = READ; \
                                    region.sh_t = NON_SHARED; \
                                    __get_section_descriptor(&descriptor_l1, region);
-
+    
 //Sect_Device_RW. Sect_Device_RO, but writeable
 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
                                    region.domain = 0x0; \
@@ -832,6 +833,7 @@ typedef enum IRQn
                                    region.user_t = RW; \
                                    region.sh_t = NON_SHARED; \
                                    __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
+    
 
 /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
 

libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h

@@ -24,45 +24,50 @@
 #endif
 /* <-Take measures about optimization problems of web compiler */
 
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
+#define DEVICE_PORTIN               1
+#define DEVICE_PORTOUT              1
+#define DEVICE_PORTINOUT            1
 
-#define DEVICE_INTERRUPTIN      1
+#define DEVICE_INTERRUPTIN          1
 
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        0
+#define DEVICE_ANALOGIN             1
+#define DEVICE_ANALOGOUT            0
 
-#define DEVICE_SERIAL           1
-#define DEVICE_SERIAL_FC        1
+#define DEVICE_SERIAL               1
+#define DEVICE_SERIAL_FC            1
+#define DEVICE_SERIAL_ASYNCH        1
 
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
+#define DEVICE_I2C                  1
+#define DEVICE_I2CSLAVE             1
+#define DEVICE_I2C_ASYNCH           1
 
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
+#define DEVICE_SPI                  1
+#define DEVICE_SPISLAVE             1
+#define DEVICE_SPI_ASYNCH           1
+#define TRANSACTION_QUEUE_SIZE_SPI 16
 
-#define DEVICE_CAN              1
+#define DEVICE_CAN                  1
 
-#define DEVICE_RTC              1
+#define DEVICE_RTC                  1
 
-#define DEVICE_ETHERNET         1
+#define DEVICE_ETHERNET             1
 
-#define DEVICE_PWMOUT           1
+#define DEVICE_PWMOUT               1
 
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       32
-#define DEVICE_MAC_OFFSET      20
+#define DEVICE_SEMIHOST             0
+#define DEVICE_LOCALFILESYSTEM      0
+#define DEVICE_ID_LENGTH            32
+#define DEVICE_MAC_OFFSET           20
 
-#define DEVICE_SLEEP            0
+#define DEVICE_SLEEP                0
 
-#define DEVICE_DEBUG_AWARENESS  0
+#define DEVICE_DEBUG_AWARENESS      0
 
-#define DEVICE_STDIO_MESSAGES   1
+#define DEVICE_STDIO_MESSAGES       1
 
-#define DEVICE_ERROR_PATTERN    1
+#define DEVICE_ERROR_PATTERN        1
 
 #include "objects.h"
+#include "dma_api.h"
 
 #endif