[Renesas RZ/A1H] Enable asynchronous communications #1626

komori-t · 2016-03-24T07:28:59Z

This enables asynchronous communications.

0xc0170 · 2016-03-24T09:09:55Z

@mtkrtk Can you please share the tests outputs for all 3 async additions (tests are under test/utest , with suffix _asynch).

komori-t · 2016-03-30T00:48:05Z

serial_async test passed.
Output is down below.

{{timeout;20}}
{{host_test_name;default_auto}}
{{description;Unit test}}
{{test_id;UT}}
{{start}}
TEST(Serial_Asynchronous, char_matching_with_complete) - 2 ms
TEST(Serial_Asynchronous, char_matching_failed) - 2 ms
TEST(Serial_Asynchronous, char_matching_success) - 1 ms
TEST(Serial_Asynchronous, rx_framing_error) - 3 ms
TEST(Serial_Asynchronous, rx_parity_error) - 1 ms
TEST(Serial_Asynchronous, long_tx_long_rx) - 2 ms
TEST(Serial_Asynchronous, short_tx_short_rx) - 1 ms
TEST(Serial_Asynchronous, short_tx_0_rx) - 0 ms

OK (8 tests, 8 ran, 28 checks, 0 ignored, 0 filtered out, 55 ms)

TomoYamanaka · 2016-03-30T04:32:24Z

Hi,

For this change difference, Renesas tearm is checking now.
Please wait for the Merge until this check work finished.

We will contact you when the timing of the check work finish is found.

Regards,
Yamanaka

0xc0170 · 2016-03-30T07:04:04Z

@TomoYamanaka Please review.

TomoYamanaka · 2016-03-30T09:01:39Z

Hi mtkrtk.

There are two questions about this change difference.

In "section_normal_sh" function defined into "MBRZA1H.h" file, please tell us about reason of
"region.sh_t = SHARED;".

(Incidentally, we understood that changes to "region.xn_t = EXECUTE;" is
required to implement the "CThunk".)
In the "mmu_Renesas_RZ_A1.c" file, although you change the "ZI_DATA" to the "Sect_Normal_SH"
only "#if defined( ICCARM )" side, we think it is necessary also to "#else" side.
how is it?

Regards,
Yamanaka

komori-t · 2016-03-30T11:09:05Z

@TomoYamanaka

In "section_normal_sh" function defined into "MBRZA1H.h" file, please tell us about reason of "region.sh_t = SHARED;".
(Incidentally, we understood that changes to "region.xn_t = EXECUTE;" is required to implement the "CThunk".)

I have no idea but without it, CThunk does not work.

In the "mmu_Renesas_RZ_A1.c" file, although you change the "ZI_DATA" to the "Sect_Normal_SH" only "#if defined( ICCARM )" side, we think it is necessary also to "#else" side. how is it?

Sorry, it is my mistake.

komori-t · 2016-03-30T11:32:05Z

Disabling MMU make it pass spi_asynch test.
MMU settings are probably wrong.
Output is down below.

{{timeout;20}}
{{host_test_name;default_auto}}
{{description;Unit test}}
{{test_id;UT}}
{{start}}
TEST(SPI_Master_Asynchronous, queue_test) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, long_tx_long_rx) - 1 ms
TEST(SPI_Master_Asynchronous, short_tx_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, 0_tx_nn_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, 0_tx_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx_nn) - 1 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx) - 1 ms

OK (9 tests, 9 ran, 36 checks, 0 ignored, 0 filtered out, 53 ms)

TomoYamanaka · 2016-03-31T11:55:17Z

@mtkrtk

We have finished the check work.

In the method of changing ZI_DATA to SHARED attribute, ZI_DATA memory becomes all non-cash state, and access speed to the memory will be reduced.
For that reason, we expect the following changes to you.

Please return to the original "Mmu_Renesas_RZ_A1.c" and "MBRZA1H.h".
Please add the following change in "MBRZA1H.h" and "CThunk.h".

https://developer.mbed.org/users/dkato/code/mbed-dev_tmp/rev/2669c14cfbea

There is no problem about the other changes.

if m_thunk is on data caches, the codes will not be executed.

komori-t · 2016-03-31T12:56:59Z

@TomoYamanaka

Thank you for the opinion. The codes are fixed

TomoYamanaka · 2016-04-01T01:16:28Z

@mtkrtk

Thank you for changing the code.
We checked the code. There is no problem.

komori-t · 2016-04-01T13:03:18Z

Individual tests are passed.
But I got a strange error while executing all the tests at once.
Output would be like

{{timeout;20}}
{{host_test_name;default_auto}}
{{description;Unit test}}
{{test_id;UT}}
{{start}}
TEST(SPI_Master_Asynchronous, queue_test)
spi_master_asynch.cpp:327: error: Failure in TEST(SPI_Master_Asynchronous, queue_test)
expected <85>
but was <85>
difference starts at position 3 at: < 85 >
^

- 24 ms
TEST(SPI_Master_Asynchronous, short_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, 0_tx_nn_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, 0_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx_nn) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx) - 0 ms
TEST(Serial_Asynchronous, char_matching_with_complete) - 2 ms
TEST(Serial_Asynchronous, char_matching_failed) - 2 ms
TEST(Serial_Asynchronous, char_matching_success) - 1 ms
TEST(Serial_Asynchronous, rx_framing_error) - 3 ms
TEST(Serial_Asynchronous, rx_parity_error) - 2 ms
TEST(Serial_Asynchronous, long_tx_long_rx) - 2 ms
TEST(Serial_Asynchronous, short_tx_short_rx)
serial_asynch.cpp:174: error: Failure in TEST(Serial_Asynchronous, short_tx_short_rx)
expected <85>
but was <86>
difference starts at position 1 at: < 86 >
^

- 25 ms
TEST(Serial_Asynchronous, short_tx_0_rx) - 0 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_pattern)

The program says 85 != 85
I put the following code at spi_master_asynch.cpp:325
dumpRXbuf();
Output would be like

{{timeout;20}}
{{host_test_name;default_auto}}
{{description;Unit test}}
{{test_id;UT}}
{{start}}
TEST(SPI_Master_Asynchronous, queue_test)
RX Buffer Contents: [50,51,52,53,54,55,56,57,58,59,5a,5b,aa,aa,aa,aa]

7 ms
TEST(SPI_Master_Asynchronous, short_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, 0_tx_nn_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, 0_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx_nn) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx) - 0 ms
TEST(Serial_Asynchronous, char_matching_with_complete) - 2 ms
TEST(Serial_Asynchronous, char_matching_failed)

The test "SPI_Master_Asynchronous, queue_test" passed, but program got freezed while executing the test "Serial_Asynchronous, char_matching_failed".
Disabling MMU make the program pass all the tests.
Output would be like

{{timeout;20}}
{{host_test_name;default_auto}}
{{description;Unit test}}
{{test_id;UT}}
{{start}}
TEST(SPI_Master_Asynchronous, queue_test) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_long_rx) - 1 ms
TEST(SPI_Master_Asynchronous, long_tx_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, long_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, 0_tx_nn_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, 0_tx_short_rx) - 1 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx_nn) - 1 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx) - 1 ms
TEST(Serial_Asynchronous, char_matching_with_complete) - 3 ms
TEST(Serial_Asynchronous, char_matching_failed) - 3 ms
TEST(Serial_Asynchronous, char_matching_success) - 2 ms
TEST(Serial_Asynchronous, rx_framing_error) - 4 ms
TEST(Serial_Asynchronous, rx_parity_error) - 3 ms
TEST(Serial_Asynchronous, long_tx_long_rx) - 2 ms
TEST(Serial_Asynchronous, short_tx_short_rx) - 1 ms
TEST(Serial_Asynchronous, short_tx_0_rx) - 1 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_pattern) - 1 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_one_byte_one_transactions) - 1 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_one_byte_separate_transactions) - 1 ms

OK (20 tests, 20 ran, 82 checks, 0 ignored, 0 filtered out, 142 ms)

{{success}}
{{end}}

Is something still wrong around MMU?

TomoYamanaka · 2016-04-06T01:31:58Z

@mtkrtk

We thought that the cause is which the contents of m_thunk was used in the previous test remain in the instruction cache.
For this reason, we expect that you try the following changes.
https://developer.mbed.org/users/dkato/code/mbed-dev_tmp/rev/ac514b5864dd

komori-t · 2016-04-07T08:40:05Z

@TomoYamanaka
Thank you for the opinion.
I tested your code, and it did not solve the problem.
But your opinion was very useful, and finally all tests are passed.
The output is down below.

{{timeout;20}}
{{host_test_name;default_auto}}
{{description;Unit test}}
{{test_id;UT}}
{{start}}
TEST(SPI_Master_Asynchronous, queue_test) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, long_tx_long_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, 0_tx_nn_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, 0_tx_short_rx) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx_nn) - 0 ms
TEST(SPI_Master_Asynchronous, short_tx_0_rx) - 0 ms
TEST(Serial_Asynchronous, char_matching_with_complete) - 2 ms
TEST(Serial_Asynchronous, char_matching_failed) - 1 ms
TEST(Serial_Asynchronous, char_matching_success) - 2 ms
TEST(Serial_Asynchronous, rx_framing_error) - 3 ms
TEST(Serial_Asynchronous, rx_parity_error) - 2 ms
TEST(Serial_Asynchronous, long_tx_long_rx) - 1 ms
TEST(Serial_Asynchronous, short_tx_short_rx) - 0 ms
TEST(Serial_Asynchronous, short_tx_0_rx) - 0 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_pattern) - 1 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_one_byte_one_transactions) - 0 ms
TEST(I2C_Master_EEPROM_Asynchronous, tx_rx_one_byte_separate_transactions) - 1 ms

OK (20 tests, 20 ran, 82 checks, 0 ignored, 0 filtered out, 130 ms)

TomoYamanaka · 2016-04-07T11:45:41Z

@mtkrtk

Thank you for changing the code.
Renesas tearm is reviewng now.

This reverts commit 621f1f1.

This reverts commit 21bd16d.

0xc0170 · 2016-04-12T10:50:31Z

Renesas tearm is reviewng now.

@TomoYamanaka @mtkrtk What's the status of this PR?

TomoYamanaka · 2016-04-12T11:59:38Z

@0xc0170

Renesas team is also reviewing to continue.

@mtkrtk

[spi_api.c]

Because the changing code have been notified the unwanted of callback to the user, Error has occurred in "queue_test" function.
We think that "__v7_clean_dcache_all" into "spi_async_write" function is not required.
Instead, we expect that you change the following line in "spi_rx_irq" function.

before:
spi_data[obj->spi.index].event = SPI_EVENT_COMPLETE;

after:
spi_data[obj->spi.index].event = SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
if (spi_data[obj->spi.index].wanted_events & SPI_EVENT_COMPLETE) {
spi_data[obj->spi.index].event |= SPI_EVENT_COMPLETE;
}

[serial_api.c]

Renesas team is reviewing now.

TomoYamanaka · 2016-04-18T05:30:15Z

@mtkrtk

We are, for the most recent pull request, lists that make the following changes.
https://developer.mbed.org/users/dkato/code/mbed-dev_tmp/rev/703108c08c7d

In SPI, modify a bug that transfer in the queue does not start when the previous transfer to the running queue_transfer() would be completed.
In Serial, modify a timing to generate TXI interrupt.

There is no problem about the other changes.

komori-t · 2016-04-18T10:48:41Z

@TomoYamanaka
Thank you for fixing the code.
With assertion codes, it does not pass the spi tests

thumb2 code executes invalid ram space, and it causes crash Add instruction cache clean codes

TomoYamanaka · 2016-04-25T09:04:13Z

@mtkrtk

Thank you for your commnets.
We made the following changes against the most recent pull request. We expect that you try the following changes. The source difference is shown the following site.
https://developer.mbed.org/users/dkato/code/mbed-dev_tmp/rev/52cd7fbf6629

[CThunk.h]

#if defined(__CORTEX_M3) ....
This instruction loads the arguments for the static thunking function to r0-r2, and branches to that function by loading its address into PC.
"ldm.w pc,{r0,r1,r2,pc}"
But, the base register must not be PC.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0489i/Cihcadda.html
So, we consider that "ldm.w pc, {r0, r1, r2, pc}" should not be used.
But it appears to operate normally, PC is loaded invalid RAM area after running for a while.
We have noticed a look at the execution history by the debugger.
In the case of Cortex-M3 / M4, it might be to work correctly, we do not try out.
In addition, because the Cortex-A is cacheable, we added the processing of cache operation.

[SPI.cpp]

If "_transaction_buffer.pop ()" has been called in "_transaction_buffer.push ()" execution, it becomes abnormal operation.
Code of "_pool [_head ++] = data;" in "push ()" operates in the following order.
However, if an interrupt in between 2 and 3 is generated, data despite not stored, "pos ()" process is executed, and returns an undefined value.
  1. Determine the address of the storage destination
  2. Increments the "_head"
  3. Store the data
So we chaned to prevent the "pop () in push ()" and "pop () in pop ()" by the disable interrupt.

komori-t · 2016-04-26T00:30:42Z

@TomoYamanaka

Thank you for changing the code.
All tests are passed with arm-none-eabi-gcc.
But it fails with armcc.
The output will be like

TEST(SPI_Master_Asynchronous, queue_test)
/src/spi_master_asynch.cpp:328: error: Failure in TEST(SPI_Master_Asynchronous, queue_test)
expected <86>
but was <255>
difference starts at position 0 at: < 255 >

I changed codes about disabling interrupts in SPI.cpp

        int was_masked;
#if defined ( __ICCARM__ )
        was_masked = __disable_irq_iar();
#else
        was_masked = __disable_irq();
#endif /* __ICCARM__ */
        _transaction_buffer.push(transaction);
        if (!spi_active(&_spi)) {
            dequeue_transaction();
        }
        if (!was_masked) {
            __enable_irq();
        }

The output was changed like

TEST(SPI_Master_Asynchronous, queue_test)
/src/spi_master_asynch.cpp:328: error: Failure in TEST(SPI_Master_Asynchronous, queue_test)
expected <86>
but was <86>
difference starts at position 4 at: < 86 >

TomoYamanaka · 2016-04-26T04:27:46Z

@mtkrtk

Sorry. We forgot to include the changes of spi_api.c that we previously chaned.
https://developer.mbed.org/users/dkato/code/mbed-dev_tmp/rev/af734d017ad0

We confirmed that these changes operate in the following environment.
https://developer.mbed.org/users/dkato/code/asynchronous_test/

komori-t · 2016-04-26T09:53:38Z

@TomoYamanaka

Thank you for pointing.
All tests are successfully passed.

0xc0170 · 2016-04-26T18:09:09Z

Ready for integration?

TomoYamanaka · 2016-04-27T00:45:44Z

@0xc0170

Yes.
Renesas tearm have completed the review. The code was fixed.

komori-t added 3 commits March 24, 2016 16:06

Add support for Cortex-A series

69c311f

Enable asynchronous communications

1df975a

Enable asynchronous communications

8a6d2b0

0xc0170 added the needs: review label Mar 24, 2016

serial_async test passed

418fd7e

komori-t added 2 commits March 30, 2016 20:24

Fix settings

2a0b000

spi_asynch test passed

9ef1d7b

spi_asynch test passed

fd02430

komori-t added 2 commits March 31, 2016 21:54

Add cache cleaning codes for Cortex-A

2586a69

if m_thunk is on data caches, the codes will not be executed.

Enable caches to improve performance

641a2dc

komori-t added 2 commits April 1, 2016 21:37

Add support for Renesas RZ/A1H

994c59d

i2c_eeprom_asynch.cpp test passed

7a9ce24

Add support for Renesas RZ/A1H

621f1f1

All async tests passed

55110c2

komori-t added 2 commits April 8, 2016 17:44

Revert "Add support for Renesas RZ/A1H"

21bd16d

This reverts commit 621f1f1.

Revert "Revert "Add support for Renesas RZ/A1H""

4f25c16

This reverts commit 21bd16d.

komori-t added 6 commits April 21, 2016 17:22

Fix cache cleaning method

6e101e0

Ensure api is active after pushing

c724a1f

Fix interrupt timings

bd5d415

Clear cache cleaning code

6d3e9e3

Change CThunk method for Cortex-A

c5422ee

thumb2 code executes invalid ram space, and it causes crash Add instruction cache clean codes

CircularBuffer::push() is critical section

50e79a4

SPI should notify internal complete

e96f6bf

0xc0170 merged commit fe9720f into ARMmbed:master Apr 29, 2016

toyowata mentioned this pull request May 17, 2016

RZ_1AH - IAR does not build #1726

Closed

[Renesas RZ/A1H] Enable asynchronous communications #1626

[Renesas RZ/A1H] Enable asynchronous communications #1626

Uh oh!

Conversation

komori-t commented Mar 24, 2016

Uh oh!

0xc0170 commented Mar 24, 2016

Uh oh!

komori-t commented Mar 30, 2016

Uh oh!

TomoYamanaka commented Mar 30, 2016

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0xc0170 commented Mar 30, 2016

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TomoYamanaka commented Mar 30, 2016

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komori-t commented Mar 30, 2016

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komori-t commented Mar 30, 2016

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TomoYamanaka commented Mar 31, 2016

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komori-t commented Mar 31, 2016

Uh oh!

TomoYamanaka commented Apr 1, 2016

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komori-t commented Apr 1, 2016

Uh oh!

TomoYamanaka commented Apr 6, 2016

Uh oh!

komori-t commented Apr 7, 2016

Uh oh!

TomoYamanaka commented Apr 7, 2016

Uh oh!

0xc0170 commented Apr 12, 2016

Uh oh!

TomoYamanaka commented Apr 12, 2016

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TomoYamanaka commented Apr 18, 2016

Uh oh!

komori-t commented Apr 18, 2016

Uh oh!

TomoYamanaka commented Apr 25, 2016

Uh oh!

komori-t commented Apr 26, 2016

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TomoYamanaka commented Apr 26, 2016

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komori-t commented Apr 26, 2016

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0xc0170 commented Apr 26, 2016

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TomoYamanaka commented Apr 27, 2016

Uh oh!

Uh oh!