STM32H7: WATCHDOG and RESET_REASON support

targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h

@@ -121,6 +121,15 @@
   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  32000U                  /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+
 /**
   * @brief External Low Speed oscillator (LSE) value.
   *        This value is used by the UART, RTC HAL module to compute the system frequency

targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c

@@ -109,10 +109,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
-   higher prescaler (256), and according to LSI variation, we need to wait at
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48u
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32H7/objects.h

@@ -170,6 +170,9 @@ struct can_s {
 #define RCC_LPUART1CLKSOURCE_PCLK1  RCC_LPUART1CLKSOURCE_PLL2
 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_LPUART1CLKSOURCE_D3PCLK1
 
+/* watchdog_api.c */
+#define IWDG IWDG1
+
 #ifdef __cplusplus
 }
 #endif

targets/TARGET_STM/reset_reason.c

@@ -27,18 +27,36 @@ reset_reason_t hal_reset_reason_get(void)
     }
 #endif
 
+#ifdef RCC_FLAG_LPWR1RST
+    if ((__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR1RST))||(__HAL_RCC_GET_FLAG(RCC_FLAG_LPWR2RST))) {
+        return RESET_REASON_WAKE_LOW_POWER;
+    }
+#endif
+
 #ifdef RCC_FLAG_WWDGRST
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)) {
         return RESET_REASON_WATCHDOG;
     }
 #endif
 
+#ifdef RCC_FLAG_WWDG1RST
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_WWDG1RST)) {
+        return RESET_REASON_WATCHDOG;
+    }
+#endif
+
 #ifdef RCC_FLAG_IWDGRST
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_IWDGRST)) {
         return RESET_REASON_WATCHDOG;
     }
 #endif
 
+#ifdef RCC_FLAG_IWDG1RST
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_IWDG1RST)) {
+        return RESET_REASON_WATCHDOG;
+    }
+#endif
+
 #ifdef RCC_FLAG_SFTRST
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_SFTRST)) {
         return RESET_REASON_SOFTWARE;
@@ -69,7 +87,11 @@ reset_reason_t hal_reset_reason_get(void)
 
 uint32_t hal_reset_reason_get_raw(void)
 {
+#if TARGET_STM32H7
+    return RCC->RSR;
+#else /* TARGET_STM32H7 */
     return RCC->CSR;
+#endif /* TARGET_STM32H7 */
 }
 
 

targets/targets.json

@@ -3227,8 +3227,7 @@
         ],
         "release_versions": ["2", "5"],
         "device_name": "STM32H743ZI",
-        "bootloader_supported": true,
-        "device_has_remove": ["WATCHDOG"]
+        "bootloader_supported": true
     },
     "NUCLEO_H743ZI2": {
         "inherits": ["NUCLEO_H743ZI"],