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Merged
merged 4 commits into from
Apr 30, 2015
Merged

Stm32cubef4 update #1076

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2ad8ff1
[STM32F4xx] update of STM32CubeF4 to version 1.5 - part 1
ohagendorf Apr 25, 2015
dbb0430
[STM32F4xx] update of STM32CubeF4 to version 1.5 - part 2
ohagendorf Apr 25, 2015
5b2d25f
[STM32F4xx] update of STM32CubeF4 to version 1.5 - part 3
ohagendorf Apr 25, 2015
03ff51f
[STM32F4xx] update of STM32CubeF4 to version 1.5 - part 4
ohagendorf Apr 25, 2015
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6 changes: 3 additions & 3 deletions ...sis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.s
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Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file startup_stm32f401xc.s
* @author MCD Application Team
* @version V2.1.0
* @date 19-June-2014
* @version V2.3.0
* @date 02-March-2015
* @brief STM32F401xCxx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
Expand All @@ -16,7 +16,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down
65 changes: 45 additions & 20 deletions ...STM32F4/TARGET_DISCO_F401VC/stm32f401xe.h → ...STM32F4/TARGET_DISCO_F401VC/stm32f401xc.h
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
/**
******************************************************************************
* @file stm32f401xe.h
* @file stm32f401xc.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-June-2014
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
* @version V2.3.0
* @date 02-March-2015
* @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
Expand All @@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -45,12 +45,12 @@
* @{
*/

/** @addtogroup stm32f401xe
/** @addtogroup stm32f401xc
* @{
*/

#ifndef __STM32F401xE_H
#define __STM32F401xE_H
#ifndef __STM32F401xC_H
#define __STM32F401xC_H

#ifdef __cplusplus
extern "C" {
Expand Down Expand Up @@ -290,8 +290,7 @@ typedef struct
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
Expand Down Expand Up @@ -536,7 +535,7 @@ typedef struct
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;

/**
* @brief __USB_OTG_Core_register
*/
Expand Down Expand Up @@ -675,7 +674,7 @@ USB_OTG_HostChannelTypeDef;
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */

/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
Expand Down Expand Up @@ -1423,6 +1422,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */

/******************* Bit definition for EXTI_EMR register *******************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Expand All @@ -1445,6 +1447,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */

/****************** Bit definition for EXTI_RTSR register *******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Expand All @@ -1467,6 +1472,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */

/****************** Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Expand All @@ -1489,6 +1497,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */

/****************** Bit definition for EXTI_SWIER register ******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Expand All @@ -1511,6 +1522,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */

/******************* Bit definition for EXTI_PR register ********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Expand All @@ -1533,6 +1547,9 @@ USB_OTG_HostChannelTypeDef;
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */

/******************************************************************************/
/* */
Expand Down Expand Up @@ -1954,7 +1971,7 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)

/****************** Bit definition for GPIO_LCKR register ********************/
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Expand Down Expand Up @@ -2125,7 +2142,7 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */

Expand Down Expand Up @@ -4511,14 +4528,14 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2C3))

/******************************** I2S Instances *******************************/
#define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))

/*************************** I2S Extended Instances ***************************/
#define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext))
#define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext))

/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Expand Down Expand Up @@ -4728,6 +4745,14 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)

/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)

/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
#define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */

/**
* @}
Expand All @@ -4745,7 +4770,7 @@ USB_OTG_HostChannelTypeDef;
}
#endif /* __cplusplus */

#endif /* __STM32F401xE_H */
#endif /* __STM32F401xC_H */



Expand Down
31 changes: 21 additions & 10 deletions libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F401VC/stm32f4xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-June-2014
* @version V2.3.0
* @date 02-March-2015
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
Expand All @@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -63,13 +63,20 @@
/** @addtogroup Library_configuration_section
* @{
*/

/**
* @brief STM32 Family
*/
#if !defined (STM32F4)
#define STM32F4
#endif /* STM32F4 */

/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE) && !defined (STM32F446xx)
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
Expand All @@ -80,9 +87,11 @@
STM32F439NI, STM32F429IG and STM32F429II Devices */
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
#define STM32F401xE /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
#define STM32F401xC /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
#endif

/* Tip: To avoid modifying this file each time you need to switch between these
Expand All @@ -94,14 +103,14 @@
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V2.1.0
* @brief CMSIS Device version number V2.3.0
*/
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
Expand Down Expand Up @@ -139,6 +148,8 @@
#include "stm32f401xe.h"
#elif defined(STM32F411xE)
#include "stm32f411xe.h"
#elif defined(STM32F446xx)
#include "stm32f446xx.h"
#else
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
#endif
Expand Down
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