FPGA SPI: remove 4 and 12 bits size support

[jeromecoutant]

Description

As it seems there is no device using this 4 and 12 size, proposition is to remove test ?

Thx

@LMESTM @c1728p9 @MarceloSalazar @ithinuel

Pull request type

[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change

[ithinuel]

Some targets such as the MK66F from NXP do support symbols from 4 to 16bits ( https://www.nxp.com/docs/en/reference-manual/K66P144M180SF5RMV2.pdf#d5667e5a1310_d11e7876 ).
The upcoming SPI api has a capability structure to declare what size are supported.

[ciarmcom]

@jeromecoutant, thank you for your changes.
@ARMmbed/mbed-os-hal @ARMmbed/mbed-os-test @ARMmbed/mbed-os-maintainers please review.

[mprse]

We do not have detailed requirements for the old SPI API which would strictly specify the defined behavior. Please consider this test as an example which shows some capabilities of the FPGA-Test-Shield.

On SPI feature branch (https://github.com/ARMmbed/mbed-os/tree/feature-hal-spec-spi) more expanded SPI test can be found.

I think that we can remove these cases, but please remove them permanently.

[0xc0170]

I think that we can remove these cases, but please remove them permanently.

+1, we got git to revert back if needed, no need to keep "dead" code

[jeromecoutant]

Dead code removed.

Seems that the revert of this PR should come in the SPI feature branch!

[jeromecoutant]

Can you start CI ?

[jamesbeyond]

CI Started

[mbed-ci]

Test run: SUCCESS

Summary: 4 of 4 test jobs passed
Build number : 1
Build artifacts

Test removed, dismissing the review.