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Stm32 ospi qspi fallback support #11291

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Merged
merged 4 commits into from
Sep 2, 2019
Merged

Stm32 ospi qspi fallback support #11291

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8401c2e
STM32: Few fixes and tidy-up in qspi_api
LMESTM Aug 28, 2019
f130724
NUCLEO_L4R5ZI : add OSPI pins for QSPI
jeromecoutant Aug 29, 2019
64b11c5
STM32 PeripheralPins generation script: add OSPI parsing
jeromecoutant Aug 29, 2019
bb1388b
NUCLEO_L4R5ZI: add QSPI_x definition
jeromecoutant Aug 29, 2019
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5 changes: 5 additions & 0 deletions targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PeripheralNames.h
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,11 @@ typedef enum {
CAN_1 = (int)CAN1_BASE
} CANName;

typedef enum {
QSPI_1 = (int)OCTOSPI1_R_BASE,
QSPI_2 = (int)OCTOSPI2_R_BASE
} QSPIName;

#ifdef __cplusplus
}
#endif
Expand Down
54 changes: 54 additions & 0 deletions targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R5xI/TARGET_NUCLEO_L4R5ZI/PeripheralPins.c
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Original file line number Diff line number Diff line change
Expand Up @@ -376,3 +376,57 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
{PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
{NC, NC, 0}
};

//*** QUADSPI ***

MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0
{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0
{PF_0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0
{PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0
{NC, NC, 0}
};

MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1
{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1
{PF_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1
{PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1
{NC, NC, 0}
};

MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2
{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2
{PF_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2
{PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2
{NC, NC, 0}
};

MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3
{PF_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3
{PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3
{NC, NC, 0}
};

MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
{PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK
{PF_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK
{PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK
{NC, NC, 0}
};

MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS
{PA_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS
{PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS
{PG_12, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS
{NC, NC, 0}
};
61 changes: 39 additions & 22 deletions targets/TARGET_STM/qspi_api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -50,24 +50,29 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef

st_command->FlashId = HAL_OSPI_FLASH_ID_1;

switch (command->instruction.bus_width) {
case QSPI_CFG_BUS_SINGLE:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
break;
case QSPI_CFG_BUS_DUAL:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES;
break;
case QSPI_CFG_BUS_QUAD:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
break;
default:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_NONE;
break;
if (command->instruction.disabled == true) {
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_NONE;
st_command->Instruction = 0;
} else {
st_command->Instruction = command->instruction.value;
switch (command->instruction.bus_width) {
case QSPI_CFG_BUS_SINGLE:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
break;
case QSPI_CFG_BUS_DUAL:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES;
break;
case QSPI_CFG_BUS_QUAD:
st_command->InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
break;
default:
error("Command param error: wrong istruction format\n");
break;
}
}

st_command->InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS;
st_command->InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
st_command->Instruction = command->instruction.value;
st_command->DummyCycles = command->dummy_count;
// these are target specific settings, use default values
st_command->SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD;
Expand All @@ -93,7 +98,7 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef
st_command->AddressMode = HAL_OSPI_ADDRESS_4_LINES;
break;
default:
st_command->AddressMode = HAL_OSPI_ADDRESS_NONE;
error("Command param error: wrong address size\n");
break;
}
switch(command->address.size) {
Expand All @@ -110,7 +115,7 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef
st_command->AddressSize = HAL_OSPI_ADDRESS_32_BITS;
break;
default:
printf("Command param error: wrong address size\n");
error("Command param error: wrong address size\n");
break;
}
}
Expand Down Expand Up @@ -284,7 +289,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN
// Set default OCTOSPI handle values
obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;
obj->handle.Init.ClockPrescaler = 4;
obj->handle.Init.ClockPrescaler = 4; // default value, will be overwritten in qspi_frequency
obj->handle.Init.FifoThreshold = 4;
obj->handle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE;
obj->handle.Init.DeviceSize = POSITION_VAL(QSPI_FLASH_SIZE_DEFAULT) - 1;
Expand Down Expand Up @@ -358,11 +363,23 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN
obj->ssel = ssel;
pinmap_pinout(ssel, PinMap_QSPI_SSEL);

OSPIM_Cfg_Struct.ClkPort = 2;
OSPIM_Cfg_Struct.DQSPort = 2;
OSPIM_Cfg_Struct.NCSPort = 2;
OSPIM_Cfg_Struct.IOLowPort = HAL_OSPIM_IOPORT_2_LOW;
OSPIM_Cfg_Struct.IOHighPort = HAL_OSPIM_IOPORT_2_HIGH;
/* The OctoSPI IO Manager OCTOSPIM configuration is supported in a simplified mode in mbed-os
* QSPI1 signals are mapped to port 1 and QSPI2 signals are mapped to port 2.
* This is coded in this way in PeripheralPins.c */
if(obj->qspi == QSPI_1) {
OSPIM_Cfg_Struct.ClkPort = 1;
OSPIM_Cfg_Struct.DQSPort = 1;
OSPIM_Cfg_Struct.NCSPort = 1;
OSPIM_Cfg_Struct.IOLowPort = HAL_OSPIM_IOPORT_1_LOW;
OSPIM_Cfg_Struct.IOHighPort = HAL_OSPIM_IOPORT_1_HIGH;
} else {
OSPIM_Cfg_Struct.ClkPort = 2;
OSPIM_Cfg_Struct.DQSPort = 2;
OSPIM_Cfg_Struct.NCSPort = 2;
OSPIM_Cfg_Struct.IOLowPort = HAL_OSPIM_IOPORT_2_LOW;
OSPIM_Cfg_Struct.IOHighPort = HAL_OSPIM_IOPORT_2_HIGH;
}

if (HAL_OSPIM_Config(&obj->handle, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
debug_if(qspi_api_c_debug, "HAL_OSPIM_Config error\n");
Expand Down
29 changes: 22 additions & 7 deletions tools/targets/STM32_gen_PeripheralPins.py
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
"""
* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
* Copyright (c) 2019 STMicroelectronics
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand All @@ -26,7 +27,7 @@
from xml.dom.minidom import parse, Node
from argparse import RawTextHelpFormatter

GENPINMAP_VERSION = "1.5"
GENPINMAP_VERSION = "1.7"

ADD_DEVICE_IF = 0
ADD_QSPI_FEATURE = 1
Expand Down Expand Up @@ -79,6 +80,7 @@
"NUCLEO_F446RE":"TIM5",
"NUCLEO_F410RB":"TIM5",
"NUCLEO_F429ZI":"TIM5",
"STM32F427V(G-I)Tx":"TIM5",
"NUCLEO_F446ZE":"TIM5",
"NUCLEO_F412ZG":"TIM5",
"NUCLEO_F413ZH":"TIM5",
Expand All @@ -99,6 +101,7 @@
"NUCLEO_L4R5ZI":"TIM5",
"NUCLEO_L4R5ZI_P":"TIM5",

"NUCLEO_WB55R":"TIM16",
"DISCO_F051R8":"TIM1",
"DISCO_F100RB":"TIM4",
"DISCO_F303VC":"TIM2",
Expand All @@ -114,7 +117,8 @@
"DISCO_L072CZ_LRWAN1":"TIM21",
"DISCO_L475VG_IOT01A":"TIM5",
"DISCO_L476VG":"TIM5",
"DISCO_L496AG":"TIM5"
"DISCO_L496AG":"TIM5",
"DISCO_L4R9A":"TIM5"
}


Expand Down Expand Up @@ -852,7 +856,10 @@ def print_qspi(l):
CommentedLine = "//"
s1 = "%-16s" % (CommentedLine + " {" + p[0] + ',')
# p[2] : QUADSPI_BK1_IO3 / QUADSPI_CLK / QUADSPI_NCS
s1 += "%-8s" % ('QSPI_1,')
if "OCTOSPIM_P2" in p[2]:
s1 += "%-8s" % ('QSPI_2,')
else:
s1 += "%-8s" % ('QSPI_1,')
result = result.replace("GPIO_AF10_OTG_FS", "GPIO_AF10_QSPI")
s1 += 'STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, ' + result +')},'
s1 += ' // ' + p[2]
Expand Down Expand Up @@ -1001,13 +1008,13 @@ def parse_pins():
store_can(pin, name, sig)
if "ETH" in sig:
store_eth(pin, name, sig)
if "QUADSPI" in sig:
if "QUADSPI" in sig or "OCTOSPI" in sig:
store_qspi(pin, name, sig)
if "USB" in sig:
store_usb(pin, name, sig)
if "RCC_OSC" in sig:
store_osc(pin, name, sig)
if "SYS_" in sig:
if "SYS_" in sig or "PWR_" in sig or "DEBUG_" in sig:
store_sys(pin, name, sig)


Expand Down Expand Up @@ -1072,6 +1079,8 @@ def parse_BoardFile(fileName):
PinLabel[EachPin] = "STDIO_UART_RX"
else:
PinLabel[EachPin] = "STDIO_UART_TX"
elif "_RESERVED" in PinLabel[EachPin]:
PinLabel[EachPin] = "RESERVED_RADIO"
except:
pass

Expand Down Expand Up @@ -1225,16 +1234,22 @@ def parse_BoardFile(fileName):
TargetName += "DISCO_"
elif "Evaluation" in board_file_name:
TargetName += "EVAL_"
m = re.search(r'STM32([\w][\dR]{3}[\w]{0,2})[\w]*_Board', board_file_name)
m = re.search(r'STM32([\w]{1,2}[\dR]{3}[\w]{0,2})[\w]*_Board', board_file_name)
if m:
TargetName += "%s" % m.group(1)
# specific case
if "-P" in args.target:
TargetName += "_P"

if "H743ZI2" in board_file_name:
TargetName += "2"

if TargetName == "DISCO_L072C":
TargetName += "Z_LRWAN1"
if TargetName == "DISCO_L475V":
elif TargetName == "DISCO_L475V":
TargetName += "G_IOT01A"
elif TargetName == "DISCO_G071RBT":
TargetName = "DISCO_G071RB"
else:
quit()

Expand Down