Differentiate alt and dummy cycles in QSPIF

TESTS/mbed_hal/qspi/qspi_test_utils.h

@@ -102,10 +102,10 @@ struct Qspi {
 #define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24
 #define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32
 
-#define ALT_SIZE_8  QSPI_CFG_ALT_SIZE_8
-#define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16
-#define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24
-#define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32
+#define ALT_SIZE_8  8u
+#define ALT_SIZE_16 16u
+#define ALT_SIZE_24 24u
+#define ALT_SIZE_32 32u
 
 #define STATUS_REG      QSPI_CMD_RDSR
 #define CONFIG_REG0      QSPI_CMD_RDCR0

components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp

@@ -36,6 +36,7 @@ using namespace mbed;
 #define UINT64_MAX -1
 #endif
 #define QSPI_NO_ADDRESS_COMMAND UINT64_MAX
+#define QSPI_ALT_DEFAULT_VALUE  0
 // Status Register Bits
 #define QSPIF_STATUS_BIT_WIP        0x1 //Write In Progress
 #define QSPIF_STATUS_BIT_WEL        0x2 // Write Enable Latch
@@ -168,12 +169,12 @@ int QSPIFBlockDevice::init()
     _inst_width = QSPI_CFG_BUS_SINGLE;
     _address_width = QSPI_CFG_BUS_SINGLE;
     _address_size = QSPI_CFG_ADDR_SIZE_24;
+    _alt_size = 0;
+    _dummy_cycles = 0;
     _data_width = QSPI_CFG_BUS_SINGLE;
-    _dummy_and_mode_cycles = 0;
     _write_register_inst = QSPIF_WRSR;
     _read_register_inst = QSPIF_RDSR;
 
-
     if (QSPI_STATUS_OK != _qspi_set_frequency(_freq)) {
         tr_error("QSPI Set Frequency Failed");
         status = QSPIF_BD_ERROR_DEVICE_ERROR;
@@ -247,7 +248,7 @@ int QSPIFBlockDevice::init()
 
     // Configure  BUS Mode to 1_1_1 for all commands other than Read
     _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
-                           QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+                           0, QSPI_CFG_BUS_SINGLE, 0);
 
     _is_initialized = true;
 
@@ -302,17 +303,17 @@ int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
     _mutex.lock();
 
     // Configure Bus for Reading
-    _qspi_configure_format(_inst_width, _address_width, _address_size, QSPI_CFG_BUS_SINGLE,
-                           QSPI_CFG_ALT_SIZE_8, _data_width, _dummy_and_mode_cycles);
+    _qspi_configure_format(_inst_width, _address_width, _address_size, _address_width, // Alt width == address width
+                           _alt_size, _data_width, _dummy_cycles);
 
     if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) {
         status = QSPIF_BD_ERROR_DEVICE_ERROR;
         tr_error("Read Command failed");
     }
 
-    // All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance less than that of the bus)
+    // All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance more than bus performance)
     _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
-                           QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+                           0, QSPI_CFG_BUS_SINGLE, 0);
 
     _mutex.unlock();
     return status;
@@ -718,7 +719,7 @@ int QSPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_
 
     // Set 1-1-1 bus mode for SFDP header parsing
     _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
-                           QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 8);
+                           0, QSPI_CFG_BUS_SINGLE, 8);
 
     qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)sfdp_header, addr /*address*/, data_length);
     if (status != QSPI_STATUS_OK) {
@@ -885,7 +886,7 @@ int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr)
 
     // Configure  BUS Mode to 1_1_1 for all commands other than Read
     _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
-                           QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+                           0, QSPI_CFG_BUS_SINGLE, 0);
 
     // Read Status Register
     if (QSPI_STATUS_OK == _qspi_send_general_command(_read_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
@@ -1024,8 +1025,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
                 read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE];
                 set_quad_enable = true;
                 is_qpi_mode = true;
-                _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5)
-                                         + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F);
+                _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F;
+                uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5;
+                _alt_size = mode_cycles * 4;
                 tr_debug("Read Bus Mode set to 4-4-4, Instruction: 0x%xh", _read_instruction);
                 //_inst_width = QSPI_CFG_BUS_QUAD;
                 _address_width = QSPI_CFG_BUS_QUAD;
@@ -1038,9 +1040,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
             //  Fast Read 1-4-4 Supported
             read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE];
             set_quad_enable = true;
-            // dummy cycles + mode cycles = Dummy Cycles
-            _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5)
-                                     + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F);
+            _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F;
+            uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5;
+            _alt_size = mode_cycles * 4;
             _address_width = QSPI_CFG_BUS_QUAD;
             _data_width = QSPI_CFG_BUS_QUAD;
             tr_debug("Read Bus Mode set to 1-4-4, Instruction: 0x%xh", _read_instruction);
@@ -1051,8 +1053,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
             //  Fast Read 1-1-4 Supported
             read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE];
             set_quad_enable = true;
-            _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5)
-                                     + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F);
+            _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F;
+            uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5;
+            _alt_size = mode_cycles;
             _data_width = QSPI_CFG_BUS_QUAD;
             tr_debug("Read Bus Mode set to 1-1-4, Instruction: 0x%xh", _read_instruction);
             break;
@@ -1061,8 +1064,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
         if (examined_byte & 0x01) {
             //  Fast Read 2-2-2 Supported
             read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE];
-            _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5)
-                                     + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F);
+            _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F;
+            uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5;
+            _alt_size = mode_cycles * 2;
             _address_width = QSPI_CFG_BUS_DUAL;
             _data_width = QSPI_CFG_BUS_DUAL;
             tr_debug("Read Bus Mode set to 2-2-2, Instruction: 0x%xh", _read_instruction);
@@ -1073,8 +1077,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
         if (examined_byte & 0x10) {
             //  Fast Read 1-2-2 Supported
             read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE];
-            _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5)
-                                     + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F);
+            _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F;
+            uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5;
+            _alt_size = mode_cycles * 2;
             _address_width = QSPI_CFG_BUS_DUAL;
             _data_width = QSPI_CFG_BUS_DUAL;
             tr_debug("Read Bus Mode set to 1-2-2, Instruction: 0x%xh", _read_instruction);
@@ -1083,8 +1088,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table
         if (examined_byte & 0x01) {
             // Fast Read 1-1-2 Supported
             read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE];
-            _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5)
-                                     + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F);
+            _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F;
+            uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5;
+            _alt_size = mode_cycles;
             _data_width = QSPI_CFG_BUS_DUAL;
             tr_debug("Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction);
             break;
@@ -1206,7 +1212,7 @@ int QSPIFBlockDevice::_enable_fast_mdoe()
 
     // Configure  BUS Mode to 1_1_1 for all commands other than Read
     _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
-                           QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0);
+                           0, QSPI_CFG_BUS_SINGLE, 0);
 
     // Read Status Register
     if (QSPI_STATUS_OK == _qspi_send_general_command(read_conf_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0,
@@ -1306,7 +1312,6 @@ int QSPIFBlockDevice::_utils_iterate_next_largest_erase_type(uint8_t &bitfield,
         tr_error("No erase type was found for current region addr");
     }
     return largest_erase_type;
-
 }
 
 /***************************************************/
@@ -1323,7 +1328,7 @@ qspi_status_t QSPIFBlockDevice::_qspi_send_read_command(unsigned int read_inst,
     // Send Read command to device driver
     size_t buf_len = size;
 
-    if (_qspi.read(read_inst, -1, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
+    if (_qspi.read(read_inst, (_alt_size == 0) ? -1 : QSPI_ALT_DEFAULT_VALUE, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) {
         tr_error("Read failed");
         return QSPI_STATUS_ERROR;
     }

components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h

@@ -357,9 +357,11 @@ class QSPIFBlockDevice : public mbed::BlockDevice {
     // Bus speed configuration
     qspi_bus_width_t _inst_width; //Bus width for Instruction phase
     qspi_bus_width_t _address_width; //Bus width for Address phase
-    qspi_address_size_t _address_size; // number of bytes for address
+    qspi_address_size_t _address_size; //Number of bits for address
+    qspi_alt_size_t _alt_size; //Number of bits for alt
+    bool _alt_enabled; //Whether alt is enabled
+    uint8_t _dummy_cycles; //Number of Dummy cycles required by Current Bus Mode
     qspi_bus_width_t _data_width; //Bus width for Data phase
-    int _dummy_and_mode_cycles; // Number of Dummy and Mode Bits required by Current Bus Mode
 
     uint32_t _init_ref_count;
     bool _is_initialized;

drivers/QSPI.h

@@ -106,7 +106,7 @@ class QSPI : private NonCopyable<QSPI> {
      *  @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
      *  @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
      *  @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
-     *  @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
+     *  @param alt_size Size in bits used by alt phase (must be a multiple of the number of bus lines indicated in alt_width)
      *  @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
      *  @param dummy_cycles Number of dummy clock cycles to be used after alt phase
      *

drivers/source/QSPI.cpp

@@ -26,6 +26,21 @@ namespace mbed {
 QSPI *QSPI::_owner = NULL;
 SingletonPtr<PlatformMutex> QSPI::_mutex;
 
+uint8_t convert_bus_width_to_line_count(qspi_bus_width_t width)
+{
+    switch (width) {
+        case QSPI_CFG_BUS_SINGLE:
+            return 1;
+        case QSPI_CFG_BUS_DUAL:
+            return 2;
+        case QSPI_CFG_BUS_QUAD:
+            return 4;
+        default:
+            // Unrecognized bus width
+            return 0;
+    }
+}
+
 QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi()
 {
     _qspi_io0 = io0;
@@ -38,7 +53,7 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
     _address_width = QSPI_CFG_BUS_SINGLE;
     _address_size = QSPI_CFG_ADDR_SIZE_24;
     _alt_width = QSPI_CFG_BUS_SINGLE;
-    _alt_size = QSPI_CFG_ALT_SIZE_8;
+    _alt_size = 0;
     _data_width = QSPI_CFG_BUS_SINGLE;
     _num_dummy_cycles = 0;
     _mode = mode;
@@ -52,7 +67,14 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin
 
 qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles)
 {
-    qspi_status_t ret_status = QSPI_STATUS_OK;
+    // Check that alt_size/alt_width are a valid combination
+    uint8_t alt_lines = convert_bus_width_to_line_count(alt_width);
+    if (alt_lines == 0) {
+        return QSPI_STATUS_ERROR;
+    } else if (alt_size % alt_lines != 0) {
+        // Invalid alt size/width combination (alt size is not a multiple of the number of bus lines used to transmit it)
+        return QSPI_STATUS_ERROR;
+    }
 
     lock();
     _inst_width = inst_width;
@@ -62,10 +84,9 @@ qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width
     _alt_size = alt_size;
     _data_width = data_width;
     _num_dummy_cycles = dummy_cycles;
-
     unlock();
 
-    return ret_status;
+    return QSPI_STATUS_OK;
 }
 
 qspi_status_t QSPI::set_frequency(int hz)

features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp

@@ -255,7 +255,7 @@ void test_direct_access_to_device_inject_root()
     ret = devkey.device_inject_root_of_trust(key, DEVICE_KEY_16BYTE);
     TEST_ASSERT_EQUAL_INT(DEVICEKEY_SUCCESS, ret);
 
-    // Now use Direct Access To DeviceKey to retrieve it */
+    // Now use Direct Access To DeviceKey to retrieve it
     uint32_t internal_start_address;
     uint32_t internal_rbp_size;
     bool is_conf_tdb_internal = false;

hal/qspi_api.h

@@ -60,12 +60,7 @@ typedef enum qspi_address_size {
 
 /** Alternative size in bits
  */
-typedef enum qspi_alt_size {
-    QSPI_CFG_ALT_SIZE_8,
-    QSPI_CFG_ALT_SIZE_16,
-    QSPI_CFG_ALT_SIZE_24,
-    QSPI_CFG_ALT_SIZE_32,
-} qspi_alt_size_t;
+typedef uint8_t qspi_alt_size_t;
 
 /** QSPI command
  *

targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c

@@ -69,21 +69,6 @@ static inline cyhal_qspi_size_t cyhal_qspi_convert_addr_size(qspi_address_size_t
     }
 }
 
-static inline cyhal_qspi_size_t cyhal_qspi_convert_alt_size(qspi_alt_size_t size)
-{
-    switch (size) {
-        case QSPI_CFG_ALT_SIZE_8:
-            return CYHAL_QSPI_CFG_SIZE_8;
-        case QSPI_CFG_ALT_SIZE_16:
-            return CYHAL_QSPI_CFG_SIZE_16;
-        case QSPI_CFG_ALT_SIZE_24:
-            return CYHAL_QSPI_CFG_SIZE_24;
-        default: // fallthrough
-        case QSPI_CFG_ALT_SIZE_32:
-            return CYHAL_QSPI_CFG_SIZE_32;
-    }
-}
-
 static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_command_t *to)
 {
     to->instruction.bus_width = cyhal_qspi_convert_width(from->instruction.bus_width);
@@ -94,7 +79,7 @@ static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_co
     to->address.value = from->address.value;
     to->address.disabled = from->address.disabled;
     to->mode_bits.bus_width = cyhal_qspi_convert_width(from->alt.bus_width);
-    to->mode_bits.size = cyhal_qspi_convert_alt_size(from->alt.size);
+    to->mode_bits.size = from->alt.size;
     to->mode_bits.value = from->alt.value;
     to->mode_bits.disabled = from->alt.disabled;
     to->dummy_count = from->dummy_count;

targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h

@@ -71,9 +71,12 @@ typedef enum {
 } cyhal_qspi_event_t;
 
 #define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/
-#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/
+#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/
+#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/
 
 /** @brief QSPI command settings */
 typedef struct cyhal_qspi_command {
@@ -90,7 +93,7 @@ typedef struct cyhal_qspi_command {
     }  address;
     struct {
         cyhal_qspi_bus_width_t bus_width;               /**< Bus width for mode bits  >*/
-        cyhal_qspi_size_t size;                         /**< Mode bits size >*/
+        uint8_t size;                                   /**< Mode bits size >*/
         uint32_t value;                                 /**< Mode bits value >*/
         bool disabled;                                  /**< Mode bits phase skipped if disabled is set to true >*/
     } mode_bits;