M263: Fix FPGA CI testing failing #11379
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NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it.
USB UART is dedicated to USB COM and so must exclude from FPGA CI testing.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API.
Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode.
Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453
Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference.
The pins suffixed with 'I2SMCLK' are for SPI I2S and cannot be used in normal SPI. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi.
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@ccli8, thank you for your changes. |
0xc0170
approved these changes
Sep 4, 2019
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CI started |
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
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Description
This PR is to pass FPGA CI test shield tests on Nuvoton NUMAKER_IOT_M263A target. It has the following major bugfix:
Related PR
Continuation of #11152 and applies on M263 target
Pull request type