TARGET_STM: L0 CUBE SPI async mode send next byte after previous one is read #12362
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…read In STM32 Cube HAL, in interrupt mode (async), 2 bytes can be prepared in hardware registers without any read (1 in regular register, the other in shift register), but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO. If interrupt handling is fast enough, each read is made in parralele of the write. But if interrupt handling is too long or is interrupted for too long, it can happen that one read byte is lost (overrun). For STM32F4, Tickless has been deactivated to avoid such issue. For STM32L0, we don't want to deactivate tickless, because those chips are specially design for lowpower. So instead of removing SPI async mode, we propose to change the HAL behavior specially for L0: each byte is send only when previous read is performed. Thus only 1 RX byte at a time which is saved in hardware register. This prevent overrun, but it introduceS some latency between each byte send, this is why it is not applied to all STM32 families.
jeromecoutant
approved these changes
Feb 4, 2020
|
@ABOSTM, thank you for your changes. |
0xc0170
approved these changes
Feb 4, 2020
|
CI started |
Test run: SUCCESSSummary: 11 of 11 test jobs passed |
0xc0170
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release-version: 6.0.0-alpha-2
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Summary of changes
TARGET_STM: L0 CUBE SPI async mode send next byte after previous one read
In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.
So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
Pull request type
Test results
test SPI ci-shield and FPGA passed on NUCLEO_L073RZ
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