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LPC1768: Fix ARM toolchain baremetal by defining 2 memory region #12369

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Merged
merged 1 commit into from
Feb 5, 2020
Merged

LPC1768: Fix ARM toolchain baremetal by defining 2 memory region #12369

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26 changes: 19 additions & 7 deletions targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -8,11 +8,22 @@
#define MBED_APP_SIZE 0x80000
#endif

#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x10000000
#endif

#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00008000
#endif

#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif

#define Stack_Size MBED_BOOT_STACK_SIZE
; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
#define VECTOR_SIZE 0xC8

#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE+0x20)

LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM0 MBED_APP_START 0x2FC { ; load address = execution address
Expand All @@ -28,20 +39,21 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
}
; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
; 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18
RW_IRAM1 0x100000C8 0x7F18-Stack_Size {
.ANY1 (+RW +ZI)
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE-0x20) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x100000C8+0x7F18) EMPTY -Stack_Size { ; stack
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x2007C000 0x4000 { ; RW data, ETH RAM
RW_IRAM2 0x2007C000 0x4000 { ; RW data, USB RAM
.ANY (AHBSRAM0)
.ANY2 (+RW +ZI)
}
RW_IRAM3 0x20080000 0x4000 { ; RW data, ETH RAM
.ANY (AHBSRAM1)
.ANY3 (+RW +ZI)
}
RW_IRAM4 0x40038000 0x0800 { ; RW data, CAN RAM
.ANY (CANRAM)
}

ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}