Update psoc6cm0p asset to 1.1.0

targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/README.md

@@ -34,6 +34,13 @@ BLESS Controller pre-built image executes the following steps:
 - starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10020000
 - goes to the while loop where processes BLE controller events and puts the CM0+ core into Deep Sleep.
 
+### New in this image
+- Updated the BLE Stack to version 5.0.6
+- Added support QFN68 and BGA124 packages.
+
+The revision history of the PSoC 6 BLE Middleware is also available on the [API Reference Guide Changelog](https://cypresssemiconductorco.github.io/bless/ble_api_reference_manual/html/page_group_ble_changelog.html).
+
+
 ### Usage
 To use this image, update the ram, flash, and FLASH_CM0P_SIZE values in the linker script for CM4:
 ```
@@ -88,6 +95,13 @@ discovered by ModusToolbox build system:
 COMPONENTS+=CM0P_BLESS
 ```
 
+Also, to operate in Dual CPU mode, add the COMPONENT_BLESS_HOST_IPC directory to 
+the list of the application level Makefile components:
+
+```
+COMPONENTS+=BLESS_HOST_IPC
+```
+
 Make sure there is a single CM0P_* component included in the COMPONENTS list
 (it might be needed to remove CM0P_SLEEP from the list of standard BSP components).
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/README.md

@@ -8,7 +8,7 @@ The Cortex M0+ application code is placed to internal flash by the Cortex M4 lin
 The Crypto server image executes the following steps:
 - configures IPC channel for data exchange between client and server applications;
 - configures three interrupts: an IPC notify interrupt, an IPC release interrupt, and an interrupt for error handling.
-- starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10008000
+- starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x1000A000
 - goes to the infinite loop that processes the crypto server events and puts the CM0+ core into Deep Sleep.
 
 ### Usage
@@ -17,21 +17,21 @@ To use this image, update the FLASH_CM0P_SIZE value in the linker script for CM4
 Example for the GCC compiler:
 ...
 /* The size and start addresses of the Cortex-M0+ application image */
-FLASH_CM0P_SIZE  = 0x8000;
+FLASH_CM0P_SIZE  = 0xA000;
 ...
 ```
 ```
 Example for the IAR compiler:
 ...
 /* The size and start addresses of the Cortex-M0+ application image */
-define symbol FLASH_CM0P_SIZE  = 0x8000;
+define symbol FLASH_CM0P_SIZE  = 0xA000;
 ...
 ```
 ```
 Example for ARMC6 compiler:
 ...
 /* The size and start addresses of the Cortex-M0+ application image */
-#define FLASH_CM0P_SIZE         0x8000
+#define FLASH_CM0P_SIZE         0xA000
 ...
 ```
 

targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml

@@ -1 +1 @@
-<version>1.0.0.35</version>
+<version>1.1.0.56</version>