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Merged
merged 6 commits into from
May 15, 2020
Merged

LPC1114: baremetal profile support #12623

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d6779bb
Support bare-metal build for NXP LPC1114
toyowata Feb 25, 2020
ab791ae
LPC1114 - linker script & startup code improvement
toyowata Mar 31, 2020
41435a0
LPC1114 - Add supported_application_modes
toyowata Apr 21, 2020
5a57670
[TESTS] Add memory check for RAM constraint device
toyowata Apr 30, 2020
9cb0391
[LPC11XX] Disable interrupt in us_ticker_init
toyowata Apr 30, 2020
58acc4e
LPC1114 - add supported_application_profiles
toyowata May 12, 2020
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5 changes: 5 additions & 0 deletions TESTS/mbed_hal/stack_size_unification/main.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,11 @@ extern uint32_t mbed_stack_isr_size;

#define EXPECTED_USER_THREAD_DEFAULT_STACK_SIZE (4096)

#if ((MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE) <= (EXPECTED_MAIN_THREAD_STACK_SIZE + EXPECTED_ISR_STACK_SIZE))
#error [NOT_SUPPORTED] Insufficient stack for staci_size_unification tests
#endif


/* Test sizes of ISR stack, main thread stack, default user thread stack.
*
* On some platforms with lower RAM size (e.g. NUCLEO_F070RB - 16 KB RAM) it is impossible
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4 changes: 4 additions & 0 deletions features/storage/TESTS/blockdevice/heap_block_device/main.cpp
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Expand Up @@ -28,6 +28,10 @@ using namespace utest::v1;
#define TEST_BLOCK_COUNT 10
#define TEST_ERROR_MASK 16

#if ((MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE) <= TEST_BLOCK_DEVICE_SIZE)
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Why is this condition different than the other two files but the comment the same?

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Because the heap_block_device test case allocates memory using TEST_BLOCK_DEVICE_SIZE.

mbed-os/features/storage/TESTS/blockdevice/heap_block_device/main.cpp

Line 45 in a707fd1

uint8_t *dummy = new (std::nothrow) uint8_t[TEST_BLOCK_DEVICE_SIZE];

And other test cases use different symbols.

mbed-os/features/storage/TESTS/blockdevice/mbr_block_device/main.cpp

Line 35 in a707fd1

uint8_t *dummy = new (std::nothrow) uint8_t[BLOCK_COUNT * BLOCK_SIZE];

#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
#endif

const struct {
const char *name;
bd_size_t (BlockDevice::*method)() const;
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4 changes: 4 additions & 0 deletions features/storage/TESTS/blockdevice/mbr_block_device/main.cpp
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Expand Up @@ -27,6 +27,10 @@ using namespace utest::v1;
#define BLOCK_COUNT 16
#define BLOCK_SIZE 512

#if ((MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE) <= (BLOCK_COUNT * BLOCK_SIZE))
#error [NOT_SUPPORTED] Insufficient heap for mbr block device tests
#endif

HeapBlockDevice bd(BLOCK_COUNT *BLOCK_SIZE, BLOCK_SIZE);

// Testing formatting of master boot record
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4 changes: 4 additions & 0 deletions features/storage/TESTS/blockdevice/util_block_device/main.cpp
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Expand Up @@ -29,6 +29,10 @@ using namespace utest::v1;
#define BLOCK_COUNT 16
#define BLOCK_SIZE 512

#if ((MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE) <= (BLOCK_COUNT * BLOCK_SIZE))
#error [NOT_SUPPORTED] Insufficient heap for util block device tests
#endif


// Simple test which read/writes blocks on a sliced block device
void test_slicing()
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43 changes: 34 additions & 9 deletions targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_ARM_STD/TARGET_LPC11XX/LPC1114.sct
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@@ -1,23 +1,48 @@
#! armcc -E

#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif

; 32K flash
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x8000
#endif

; 4KB
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x10000000
#endif

#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x00001000
#endif


#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#define MBED_BOOT_STACK_SIZE 0x400
#endif

#define Stack_Size MBED_BOOT_STACK_SIZE
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
#define VECTOR_SIZE 0xC0

#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)

LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
ER_IROM1 0x00000000 0x8000 { ; load address = execution address
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region

ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
; 8KB - 0xC0 = 0xF40
RW_IRAM1 0x100000C0 0xF40-Stack_Size {

RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK (0x100000C0+0xF40) EMPTY -Stack_Size { ; stack

ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}

ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}
20 changes: 10 additions & 10 deletions targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_ARM/TARGET_LPC11XX/LPC1114.ld
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Expand Up @@ -46,9 +46,9 @@ SECTIONS
.text :
{
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
*(.text.Reset_Handler)
*(.text.SystemInit)
. = 0x200;
. = 0x200;
*(.text*)

KEEP(*(.init))
Expand Down Expand Up @@ -95,24 +95,24 @@ SECTIONS

. = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
PROVIDE_HIDDEN (__preinit_array_end = .);

. = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
PROVIDE_HIDDEN (__init_array_end = .);


. = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
PROVIDE_HIDDEN (__fini_array_end = .);

. = ALIGN(8);
/* All data end */
Expand All @@ -128,7 +128,7 @@ SECTIONS
__bss_end__ = .;
} > RAM

.heap :
.heap (COPY):
{
__end__ = .;
end = __end__;
Expand All @@ -140,7 +140,7 @@ SECTIONS
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
.stack_dummy (COPY):
{
*(.stack)
} > RAM
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31 changes: 0 additions & 31 deletions targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_ARM/startup_LPC11xx.S
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Expand Up @@ -44,36 +44,7 @@
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x80
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop

.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x80
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit

.section .isr_vector
.align 2
.globl __isr_vector
Expand Down Expand Up @@ -210,7 +181,5 @@ Reset_Handler:
def_irq_default_handler PIOINT2_IRQHandler
def_irq_default_handler PIOINT1_IRQHandler
def_irq_default_handler PIOINT0_IRQHandler
def_irq_default_handler DEF_IRQHandler

.end

5 changes: 3 additions & 2 deletions targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/cmsis_nvic.c
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Expand Up @@ -60,8 +60,9 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;

// Copy and switch to dynamic vectors if first time called
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
// Add volatile qualifier to avoid armclang aggressive optimization
volatile uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
for(i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
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3 changes: 3 additions & 0 deletions targets/TARGET_NXP/TARGET_LPC11XX_11CXX/us_ticker.c
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Expand Up @@ -23,6 +23,9 @@
int us_ticker_inited = 0;

void us_ticker_init(void) {
// First, disabled interrupt
US_TICKER_TIMER->MCR &= ~1;

if (us_ticker_inited) return;
us_ticker_inited = 1;

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27 changes: 20 additions & 7 deletions targets/targets.json
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Expand Up @@ -266,7 +266,7 @@
"LPCTarget"
],
"core": "Cortex-M0",
"default_toolchain": "uARM",
"default_toolchain": "ARM",
"extra_labels": [
"NXP",
"LPC11XX_11CXX",
Expand All @@ -278,7 +278,6 @@
],
"supported_toolchains": [
"ARM",
"uARM",
"GCC_ARM",
"IAR"
],
Expand All @@ -295,12 +294,26 @@
"SLEEP",
"SPI",
"SPISLAVE",
"STDIO_MESSAGES"
],
"default_lib": "small",
"release_versions": [
"2"
"STDIO_MESSAGES",
"USTICKER"
],
"overrides": {
"tickless-from-us-ticker": true,
"boot-stack-size": "0x300"
},
"supported_c_libs": {
"arm": [
"std", "small"
],
"gcc_arm": [
"std", "small"
],
"iar": [
"std"
]
},
"c_lib": "small",
"supported_application_profiles": ["bare-metal"],
"device_name": "LPC1114FN28/102",
"detect_code": [
"1114"
Expand Down