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Merged
merged 7 commits into from
May 11, 2020
Merged

[feature-wisun] Nanostack release 12.2.0 #12950

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1687b4a
Squashed 'features/nanostack/sal-stack-nanostack/' changes from cc032…
May 11, 2020
314eb7a
Merge commit '1687b4aa4f8e24dffa1b019757c081da48bf526d' into feature-…
May 11, 2020
4b041bf
Squashed 'features/frameworks/nanostack-libservice/' changes from 9a6…
May 11, 2020
cb94e60
Merge commit '4b041bf749b46884727bf627a1a73da6d756ccd9' into feature-…
May 11, 2020
e37631d
802.15.4 STM S2LP driver update
May 11, 2020
046af8f
802.15.4 Atmel RF driver update
May 11, 2020
eeaa917
802.15.4 MCR20A RF driver update
May 11, 2020
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40 changes: 40 additions & 0 deletions components/802.15.4_RF/atmel-rf-driver/source/AT86RF215Reg.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,9 @@ extern "C" {
#define BBC_TXFLH 0x07
#define BBC_FBLL 0x08
#define BBC_FBLH 0x09
#define BBC_OFDMPHRTX 0x0C
#define BBC_OFDMC 0x0E
#define BBC_OFDMSW 0x0F
#define BBC_OQPSKC0 0x10
#define BBC_OQPSKC1 0x11
#define BBC_OQPSKC2 0x12
Expand Down Expand Up @@ -90,6 +93,7 @@ extern "C" {
// RF_AGCS
#define TGT 0xE0
#define TGT_1 (1 << 5)
#define TGT_3 (3 << 5)


// RF_RXBWC
Expand Down Expand Up @@ -131,6 +135,7 @@ extern "C" {
// RF_TXDFE, RF_RXDFE
#define RCUT 0xE0
#define RCUT_4 (4 << 5)
#define RCUT_3 (3 << 5)
#define RCUT_2 (2 << 5)
#define RCUT_1 (1 << 5)
#define RCUT_0 (0 << 5)
Expand All @@ -144,6 +149,41 @@ extern "C" {
#define SR_2 (2 << 0)
#define SR_1 (1 << 0)

// BBC_OFDMPHRTX
#define MCS 0x07
#define MCS_0 (0 << 0)
#define MCS_1 (1 << 0)
#define MCS_2 (2 << 0)
#define MCS_3 (3 << 0)
#define MCS_4 (4 << 0)
#define MCS_5 (5 << 0)
#define MCS_6 (6 << 0)

// BBC_OFDMC
#define SSRX 0xC0
#define SSRX_0 (0 << 6)
#define SSRX_1 (1 << 6)
#define SSRX_2 (2 << 6)
#define SSRX_3 (3 << 6)
#define SSTX 0x30
#define SSTX_0 (0 << 4)
#define SSTX_1 (1 << 4)
#define SSTX_2 (2 << 4)
#define SSTX_3 (3 << 4)
#define LFO (1 << 3)
#define POI (1 << 2)
#define OPT 0x03
#define OPT_1 (0 << 0)
#define OPT_2 (1 << 0)
#define OPT_3 (2 << 0)
#define OPT_4 (3 << 0)

// BBC_OFDMSW
#define OFDM_PDT 0xE0
#define OFDM_PDT_5 (5 << 5)
#define OFDM_PDT_4 (4 << 5)
#define OFDM_PDT_3 (3 << 5)

// BBC_FSKC0
#define BT 0xC0
#define BT_20 (3 << 6)
Expand Down
163 changes: 129 additions & 34 deletions components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAT86RF215.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -99,6 +99,7 @@ static int rf_set_channel(uint16_t channel, rf_modules_e module);
static int rf_set_ch0_frequency(uint32_t frequency, rf_modules_e module);
static int rf_set_channel_spacing(uint32_t channel_spacing, rf_modules_e module);
static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules_e module);
static int rf_configure_by_ofdm_bandwidth_option(uint8_t option, uint32_t data_rate, rf_modules_e module);
static void rf_calculate_symbol_rate(uint32_t baudrate, phy_modulation_e modulation);
static void rf_conf_set_cca_threshold(uint8_t percent);
// Defined register read/write functions
Expand Down Expand Up @@ -300,6 +301,9 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
case PHY_EXTENSION_SET_CCA_THRESHOLD:
rf_conf_set_cca_threshold(*data_ptr);
break;
case PHY_EXTENSION_SET_CHANNEL_CCA_THRESHOLD:
cca_threshold = (int8_t) *data_ptr; // *NOPAD*
break;
case PHY_EXTENSION_SET_802_15_4_MODE:
mac_mode = (phy_802_15_4_mode_t) *data_ptr; // *NOPAD*
if (mac_mode == IEEE_802_15_4_2011) {
Expand Down Expand Up @@ -378,7 +382,8 @@ static void rf_init(void)
static void rf_init_registers(rf_modules_e module)
{
// O-QPSK configuration using IEEE Std 802.15.4-2011
// FSK configuration using IEEE Std 802.15.4g-2012
// FSK/OFDM configuration using IEEE Std 802.15.4g-2012
// OFDM configuration is experimental only
if (mac_mode == IEEE_802_15_4_2011) {
device_driver.link_type = PHY_LINK_15_4_2_4GHZ_TYPE;
// 16-bit FCS
Expand All @@ -405,40 +410,59 @@ static void rf_init_registers(rf_modules_e module)
rf_write_bbc_register_field(BBC_AFFTM, module, TYPE_2, TYPE_2);
} else if (mac_mode == IEEE_802_15_4G_2012) {
device_driver.link_type = PHY_LINK_15_4_SUBGHZ_TYPE;
// Enable FSK
rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK);
// Disable auto ack
rf_write_bbc_register_field(BBC_AMCS, module, AACK, 0);
// Disable address filter unit 0
rf_write_bbc_register_field(BBC_AFC0, module, AFEN0, 0);
// Set bandwidth time product
rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20);
// Disable interleaving
rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0);
// Disable receiver override
rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS);
// Set modulation index
if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) {
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0);
} else {
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
}
// Set Gain control settings
rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1);
// Set symbol rate and related configurations
rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module);
// Set preamble length
uint8_t preamble_len = 24;
if (phy_current_config.datarate < 150000) {
preamble_len = 8;
} else if (phy_current_config.datarate < 300000) {
preamble_len = 12;
// Enable FSK
if (phy_current_config.modulation == M_2FSK) {
rf_write_bbc_register_field(BBC_PC, module, PT, BB_MRFSK);
// Set bandwidth time product
rf_write_bbc_register_field(BBC_FSKC0, module, BT, BT_20);
// Disable interleaving
rf_write_bbc_register_field(BBC_FSKC2, module, FECIE, 0);
// Disable receiver override
rf_write_bbc_register_field(BBC_FSKC2, module, RXO, RXO_DIS);
// Set modulation index
if (phy_current_config.modulation_index == MODULATION_INDEX_0_5) {
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_05);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_0);
} else {
rf_write_bbc_register_field(BBC_FSKC0, module, MIDX, MIDX_10);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
}
// Set Gain control settings
rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_1);
// Set symbol rate and related configurations
rf_set_fsk_symbol_rate_configuration(phy_current_config.datarate, module);
// Set preamble length
uint8_t preamble_len = 24;
if (phy_current_config.datarate < 150000) {
preamble_len = 8;
} else if (phy_current_config.datarate < 300000) {
preamble_len = 12;
}
rf_write_bbc_register(BBC_FSKPLL, module, preamble_len);
// Set preamble detector threshold
rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6);
} else if (phy_current_config.modulation == M_OFDM) {
rf_write_bbc_register_field(BBC_PC, module, PT, BB_MROFDM);
// Set TX scrambler seed
rf_write_bbc_register_field(BBC_OFDMC, module, SSTX, SSTX_0);
// Set RX scrambler seed
rf_write_bbc_register_field(BBC_OFDMC, module, SSRX, SSRX_0);
// Set phyOFDMInterleaving
rf_write_bbc_register_field(BBC_OFDMC, module, POI, 0);
// Set low frequency offset bit
rf_write_bbc_register_field(BBC_OFDMC, module, LFO, 0);
// Configure using bandwidth option
rf_configure_by_ofdm_bandwidth_option(4, 300000, module);
// Set Gain control settings
rf_write_rf_register_field(RF_AGCC, module, AVGS, AVGS_8_SAMPLES);
rf_write_rf_register_field(RF_AGCC, module, AGCI, 0);
rf_write_rf_register_field(RF_AGCS, module, TGT, TGT_3);
}
rf_write_bbc_register(BBC_FSKPLL, module, preamble_len);
rf_write_bbc_register_field(BBC_FSKC3, module, PDT, PDT_6);
}
// Disable filtering FCS
rf_write_bbc_register_field(BBC_PC, module, FCSFE, 0);
Expand Down Expand Up @@ -488,9 +512,10 @@ static int8_t rf_start_csma_ca(uint8_t *data_ptr, uint16_t data_length, uint8_t
tx_sequence = *(data_ptr + 2);
}
rf_write_tx_buffer(data_ptr, data_length, rf_module);
if (phy_current_config.modulation == M_OQPSK) {
// Add CRC bytes
if (mac_mode == IEEE_802_15_4_2011) {
data_length += 2;
} else if (phy_current_config.modulation == M_2FSK) {
} else {
data_length += 4;
}
rf_write_tx_packet_length(data_length, rf_module);
Expand Down Expand Up @@ -614,9 +639,10 @@ static void rf_handle_rx_done(void)
rf_handle_ack(rx_buffer[2], rx_buffer[0] & MAC_DATA_PENDING);
} else {
int8_t rssi = (int8_t) rf_read_rf_register(RF_EDV, rf_module);
if (phy_current_config.modulation == M_OQPSK) {
// Cut CRC bytes
if (mac_mode == IEEE_802_15_4_2011) {
cur_rx_packet_len -= 2;
} else if (phy_current_config.modulation == M_2FSK) {
} else {
cur_rx_packet_len -= 4;
}
device_driver.phy_rx_cb(rx_buffer, cur_rx_packet_len, 0xf0, rssi, rf_radio_driver_id);
Expand Down Expand Up @@ -1055,6 +1081,75 @@ static int rf_set_fsk_symbol_rate_configuration(uint32_t symbol_rate, rf_modules
return 0;
}

static int rf_configure_by_ofdm_bandwidth_option(uint8_t option, uint32_t data_rate, rf_modules_e module)
{
if (!option || option > 4) {
return -1;
}
uint32_t datarate_tmp = 100000 >> (option - 1);

// Set modulation and coding scheme
if (data_rate == datarate_tmp) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_0);
} else if (data_rate == datarate_tmp * 2) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_1);
} else if (data_rate == datarate_tmp * 4) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_2);
} else if (data_rate == datarate_tmp * 8) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_3);
} else if (data_rate == datarate_tmp * 12) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_4);
} else if (data_rate == datarate_tmp * 16) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_5);
} else if (data_rate == datarate_tmp * 24) {
rf_write_bbc_register_field(BBC_OFDMPHRTX, module, MCS, MCS_6);
} else {
return -1;
}
if (option == 1) {
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_1);
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_3);
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_3);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_4);
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_4);
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC800KHZ);
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW1250KHZ_IF2000KHZ);
rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS);
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_5);
} else if (option == 2) {
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_2);
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_3);
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_3);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_3);
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2);
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC500KHZ);
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW800KHZ_IF1000KHZ);
rf_write_rf_register_field(RF_RXBWC, module, IFS, IFS);
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_5);
} else if (option == 3) {
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_3);
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_6);
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_6);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_3);
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_2);
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC250KHZ);
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW400KHZ_IF500KHZ);
rf_write_rf_register_field(RF_RXBWC, module, IFS, 0);
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_4);
} else if (option == 4) {
rf_write_bbc_register_field(BBC_OFDMC, module, OPT, OPT_4);
rf_write_rf_register_field(RF_TXDFE, module, SR, SR_6);
rf_write_rf_register_field(RF_RXDFE, module, SR, SR_6);
rf_write_rf_register_field(RF_TXDFE, module, RCUT, RCUT_2);
rf_write_rf_register_field(RF_RXDFE, module, RCUT, RCUT_1);
rf_write_rf_register_field(RF_TXCUTC, module, LPFCUT, RF_FLC160KHZ);
rf_write_rf_register_field(RF_RXBWC, module, BW, RF_BW250KHZ_IF250KHZ);
rf_write_rf_register_field(RF_RXBWC, module, IFS, 1);
rf_write_bbc_register_field(BBC_OFDMSW, module, OFDM_PDT, OFDM_PDT_3);
}
return 0;
}

static void rf_conf_set_cca_threshold(uint8_t percent)
{
uint8_t step = (MAX_CCA_THRESHOLD - MIN_CCA_THRESHOLD);
Expand Down
5 changes: 1 addition & 4 deletions components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* \file MCR20Drv.c
*
Expand Down Expand Up @@ -114,9 +115,7 @@ void MCR20Drv_Init
xcvr_spi_configure_speed(gXcvrSpiInstance_c, 8000000);

gXcvrDeassertCS_d();
#if !defined(TARGET_KW24D)
MCR20Drv_RST_B_Deassert();
#endif
RF_IRQ_Init();
RF_IRQ_Disable();
mPhyIrqDisableCnt = 1;
Expand Down Expand Up @@ -639,7 +638,6 @@ void MCR20Drv_RESET
void
)
{
#if !defined(TARGET_KW24D)
volatile uint32_t delay = 1000;
//assert RST_B
MCR20Drv_RST_B_Assert();
Expand All @@ -648,7 +646,6 @@ void MCR20Drv_RESET

//deassert RST_B
MCR20Drv_RST_B_Deassert();
#endif
}

/*---------------------------------------------------------------------------
Expand Down
1 change: 1 addition & 0 deletions components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Drv.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* \file MCR20Drv.h
*
Expand Down
1 change: 1 addition & 0 deletions components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Overwrites.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* \file MCR20Overwrites.h
* Description: Overwrites header file for MCR20 Register values
Expand Down
1 change: 1 addition & 0 deletions components/802.15.4_RF/mcr20a-rf-driver/source/MCR20Reg.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* \file MCR20reg.h
* MCR20 Registers
Expand Down
8 changes: 1 addition & 7 deletions components/802.15.4_RF/mcr20a-rf-driver/source/NanostackRfPhyMcr20a.cpp
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Expand Up @@ -61,11 +61,7 @@ extern "C" {
#define gCcaCCA_MODE1_c 1

#define gXcvrRunState_d gXcvrPwrAutodoze_c
#if !defined(TARGET_KW24D)
#define gXcvrLowPowerState_d gXcvrPwrHibernate_c
#else
#define gXcvrLowPowerState_d gXcvrPwrAutodoze_c
#endif

namespace {

Expand Down Expand Up @@ -504,9 +500,7 @@ static void rf_init(void)
/* Disable Tristate on MISO for SPI reads */
MCR20Drv_IndirectAccessSPIWrite(MISC_PAD_CTRL, 0x02);
/* Set XCVR clock output settings */
#if !defined(TARGET_KW24D)
MCR20Drv_Set_CLK_OUT_Freq(gMCR20_ClkOutFreq_d);
#endif
/* Set default XCVR power state */
rf_set_power_state(gXcvrRunState_d);

Expand Down Expand Up @@ -1758,7 +1752,7 @@ void NanostackRfPhyMcr20a::_pins_clear()
irq_thread = NULL;
}

#if MBED_CONF_MCR20A_PROVIDE_DEFAULT || TARGET_KW24D
#if MBED_CONF_MCR20A_PROVIDE_DEFAULT

NanostackRfPhy &NanostackRfPhy::get_default_instance()
{
Expand Down
1 change: 1 addition & 0 deletions components/802.15.4_RF/mcr20a-rf-driver/source/XcvrSpi.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
/*!
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
* SPDX-License-Identifier: BSD-3-Clause
*
* \file XcvrSpi.h
*
Expand Down
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