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Cypress: Add target CY8CKIT_064B0S2_4343W, update psoc6pdl, psoc6cm0p #13122

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Merged
merged 25 commits into from
Jun 24, 2020
Merged

Cypress: Add target CY8CKIT_064B0S2_4343W, update psoc6pdl, psoc6cm0p #13122

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4700a72
Update psoc6pdl to 1.6.0.3875
romanjoe Jun 10, 2020
683e363
Update psoc6cm0p to 1.2.0.174
romanjoe Jun 10, 2020
bdac29e
Add 064B0S2 target BSP files using psoc6pdl 1.6.0.3875
romanjoe Jun 10, 2020
571e097
Add secure cm0 psoc6cm0p hex prebuild 1.2.0.174 file to 064B0S2 BSP
romanjoe Jun 10, 2020
64a3d26
Delete ES10 target source CY8CPROTO_064_SB
romanjoe Jun 10, 2020
07bf595
Delete ES10 target source CYESKIT_064B0S2_4343W
romanjoe Jun 10, 2020
c97f140
Delete ES10 target source CY8CKIT_064S2_4343W
romanjoe Jun 10, 2020
773a4be
Delete ES10 targets from targets.json
romanjoe Jun 10, 2020
b59a80d
Add 064B0S2 target to targets.json
romanjoe Jun 10, 2020
f689c05
Modify post build scripts to support only cysecuretools signing
romanjoe Jun 10, 2020
edcda51
Delete ES10 related sb-tools folder from TARGET_PSOC6, post build now…
romanjoe Jun 10, 2020
797bf09
Delete policies and linker files for multi image for B0S2
romanjoe Jun 12, 2020
9be0baf
Remove ES10 targets from flash_config header in tests, remove mbed_ap…
romanjoe Jun 15, 2020
aa3c81e
Update psoc6pdl to .1.6.0.4172 RC2
romanjoe Jun 15, 2020
f99a1c4
Update GeneratedSource and system files for B0S2 using psoc6pdl 1.6.0…
romanjoe Jun 15, 2020
66f6e2a
Update asset psoc6cm0p build 1.2.0.210 RC1
romanjoe Jun 15, 2020
fc42c74
Rework find_policy() in post build script to enable default locations
romanjoe Jun 15, 2020
4043dee
Update linker scripts with templates from psoc6pdl 1.6.0.4172 for IAR…
romanjoe Jun 16, 2020
2a313c3
Update prebuild Secure CM0p hex file from multi image case with 064B0…
romanjoe Jun 16, 2020
bcc8c2c
Rename 064B0S2 linker scripts names per common pattern
romanjoe Jun 17, 2020
7a862d2
Update psoc6pdl to 1.6.0.4266-rc3
romanjoe Jun 18, 2020
611c956
Update psoc6cm0p to 1.2.0.237-rc2
romanjoe Jun 18, 2020
1bd215b
Update GeneratedSource files for 064B0S2 using psoc6pdl-1.6.0.4266-rc3
romanjoe Jun 18, 2020
dcc3559
Update GeneratedSources for 064B0S2 - disable ALT systick due to chan…
romanjoe Jun 18, 2020
00cbc2d
Update GeneratedSource of 064B0S2 with repo-starging 15347 revision
romanjoe Jun 18, 2020
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5 changes: 1 addition & 4 deletions TESTS/mbed_hal/qspi/flash_configs/flash_configs.h
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Expand Up @@ -67,7 +67,7 @@
defined(TARGET_CY8CKIT_062S2_43012) || \
defined(TARGET_CY8CKIT_062S2_4343W) || \
defined(TARGET_CY8CKIT_064S2_4343W) || \
defined(TARGET_CYESKIT_064B0S2_4343W) || \
defined(TARGET_CY8CKIT_064B0S2_4343W) || \
defined(TARGET_CY8CPROTO_062_4343W) || \
defined(TARGET_CY8CPROTO_062S2_43012) || \
defined(TARGET_CY8CPROTO_062S3_4343W) || \
Expand All @@ -78,9 +78,6 @@
#elif defined(TARGET_CYW9P62S1_43012EVB_01)
#include "S25FS512S_config.h"

#elif defined(TARGET_CY8CPROTO_064_SB)
#include "S25FL128S_config.h"

#endif

#endif // MBED_FLASH_CONFIGS_H
4 changes: 2 additions & 2 deletions ..._BSP_DESIGN_MODUS/GeneratedSource/cycfg.c → ..._BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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Expand Up @@ -4,8 +4,8 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down
4 changes: 2 additions & 2 deletions ..._BSP_DESIGN_MODUS/GeneratedSource/cycfg.h → ..._BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
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Expand Up @@ -4,8 +4,8 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down
52 changes: 26 additions & 26 deletions ...IGN_MODUS/GeneratedSource/cycfg.timestamp → ...IGN_MODUS/GeneratedSource/cycfg.timestamp
100755 → 100644
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@@ -1,26 +1,26 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
6 changes: 3 additions & 3 deletions ...SIGN_MODUS/GeneratedSource/cycfg_clocks.c → ...SIGN_MODUS/GeneratedSource/cycfg_clocks.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand All @@ -27,7 +27,7 @@
#include "cycfg_clocks.h"

#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
Expand Down
4 changes: 2 additions & 2 deletions ...SIGN_MODUS/GeneratedSource/cycfg_clocks.h → ...SIGN_MODUS/GeneratedSource/cycfg_clocks.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down
4 changes: 2 additions & 2 deletions ...IGN_MODUS/GeneratedSource/cycfg_notices.h → ...IGN_MODUS/GeneratedSource/cycfg_notices.h
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,8 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down
6 changes: 3 additions & 3 deletions ...MODUS/GeneratedSource/cycfg_peripherals.c → ...MODUS/GeneratedSource/cycfg_peripherals.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down Expand Up @@ -34,5 +34,5 @@ cy_stc_csd_context_t cy_csd_0_context =

void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
}
8 changes: 4 additions & 4 deletions ...MODUS/GeneratedSource/cycfg_peripherals.h → ...MODUS/GeneratedSource/cycfg_peripherals.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down Expand Up @@ -37,8 +37,8 @@ extern "C" {

#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 96000000u
#define CY_CAPSENSE_PERI_CLK 48000000u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
Expand Down
16 changes: 8 additions & 8 deletions ...DESIGN_MODUS/GeneratedSource/cycfg_pins.c → ...DESIGN_MODUS/GeneratedSource/cycfg_pins.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (libs/psoc6pdl): 1.4.1.2240
* cfg-backend-cli: 1.2.0.1483
* Device Support Library (libs/psoc6pdl): 1.6.0.4266
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
Expand Down Expand Up @@ -74,11 +74,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_CSD_TX_HSIOM,
.hsiom = CYBSP_CSD_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
Expand All @@ -91,11 +91,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
.block_num = CYBSP_CSD_RX_PORT_NUM,
.channel_num = CYBSP_CSD_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
Expand Down Expand Up @@ -425,7 +425,7 @@ void init_cycfg_pins(void)
#endif //defined (CY_USING_HAL)

#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
#endif //defined (CY_USING_HAL)

Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
Expand Down
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