Skip to content

[feature-wisun] targets:RT1050: Fix the low speed switch issue #13526

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 2, 2020
Merged

[feature-wisun] targets:RT1050: Fix the low speed switch issue #13526

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 7 additions & 1 deletion targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/specific.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,11 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
case LPM_PowerModeLowSpeedRun:
case LPM_PowerModeSysIdle:
CLOCK_SET_DIV(kCLOCK_SemcDiv, 3); // SEMC CLK should not exceed 166MHz
#ifdef HYPERFLASH_BOOT
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 1); // FLEXSPI in DDR mode
#else
CLOCK_SET_DIV(kCLOCK_FlexspiDiv, 3); // FLEXSPI in SDR mode
#endif
CLOCK_SET_MUX(kCLOCK_FlexspiMux, 2); // FLEXSPI mux to PLL2 PFD2
/* CORE CLK to 132MHz and AHB, IPG, PERCLK to 33MHz */
CLOCK_SET_DIV(kCLOCK_PerclkDiv, 0);
Expand Down Expand Up @@ -108,6 +112,7 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
/* Enable clock gate of flexspi. */
CCM->CCGR6 |= (CCM_CCGR6_CG5_MASK);

#ifdef HYPERFLASH_BOOT
if ((LPM_PowerModeLowPowerRun == power_mode) || (LPM_PowerModeLPIdle == power_mode))
{
FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(19);
Expand All @@ -116,7 +121,8 @@ void SwitchSystemClocks(lpm_power_mode_t power_mode)
{
FLEXSPI_INST->DLLCR[0] = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(15);
}

#endif

FLEXSPI_INST->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
FLEXSPI_INST->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
while (FLEXSPI_INST->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
Expand Down