Add support for MIMXRT1170_EVK

storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json

@@ -26,6 +26,10 @@
         "MIMXRT1050_EVK": {
             "base-address": "0x60400000",
             "size": "0x3C00000"
+        },
+        "MIMXRT1170_EVK": {
+            "base-address": "0x60000000",
+            "size": "0x7F00000"
         }
     }
 }

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/CMakeLists.txt

@@ -6,6 +6,7 @@ add_subdirectory(TARGET_LPC EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_LPC54114 EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MCU_LPC546XX EXCLUDE_FROM_ALL)
 add_subdirectory(TARGET_MIMXRT1050 EXCLUDE_FROM_ALL)
+add_subdirectory(TARGET_MIMXRT1170 EXCLUDE_FROM_ALL)
 add_subdirectory(middleware/TARGET_USB EXCLUDE_FROM_ALL)
 
 add_library(mbed-mcuxpresso-mcus INTERFACE)

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/CMakeLists.txt

@@ -10,20 +10,14 @@ target_include_directories(mbed-imx
 
 target_sources(mbed-imx
     INTERFACE
-        analogin_api.c
-        flash_api.c
         gpio_api.c
         gpio_irq_api.c
         i2c_api.c
         lp_ticker.c
-        pinmap.c
         port_api.c
         pwmout_api.c
         rtc_api.c
-        serial_api.c
         sleep.c
         spi_api.c
-        trng_api.c
-        us_ticker.c
         watchdog_api.c
 )

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/CMakeLists.txt

@@ -11,12 +11,18 @@ target_include_directories(mbed-evk
 
 target_sources(mbed-evk
     INTERFACE
-        PeripheralPins.c
+        flash_api.c
         fsl_clock_config.c
         fsl_phy.c
         lpm.c
         mbed_overrides.c
+        PeripheralPins.c
+        pinmap.c
+        serial_api.c
         specific.c
+        trng_api.c
+        us_ticker.c
+
 
         xip/evkbimxrt1050_flexspi_nor_config.c
         xip/evkbimxrt1050_sdram_ini_dcd.c

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt

@@ -0,0 +1,52 @@
+# Copyright (c) 2020-2021 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(TARGET_EVK EXCLUDE_FROM_ALL)
+
+if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
+    set(STARTUP_FILE device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1176_cm7.S)
+    set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/MIMXRT1170xxxxx.ld)
+endif()
+
+add_library(mbed-mimxrt1170-evk INTERFACE)
+
+target_include_directories(mbed-mimxrt1170-evk
+    INTERFACE
+        .
+        device
+        drivers
+)
+
+target_sources(mbed-mimxrt1170-evk
+    INTERFACE
+
+        device/system_MIMXRT1176_cm7.c
+
+        drivers/fsl_lpadc.c
+        drivers/fsl_anatop.c
+        drivers/fsl_anatop_ai.c
+        drivers/fsl_cache.c
+        drivers/fsl_clock.c
+        drivers/fsl_common.c
+        drivers/fsl_dcdc.c
+        drivers/fsl_flexspi.c
+        drivers/fsl_flexspi_nor_boot.c
+        drivers/fsl_gpio.c
+        drivers/fsl_lpi2c.c
+        drivers/fsl_lpspi.c
+        drivers/fsl_lpuart.c
+        drivers/fsl_pmu.c
+        drivers/fsl_pwm.c
+        drivers/fsl_xbara.c
+
+        ${STARTUP_FILE}
+)
+
+target_link_libraries(mbed-mimxrt1170-evk
+    INTERFACE
+        mbed-mcuxpresso-mcus
+        mbed-evk-rt1170
+        mbed-imx
+)
+
+mbed_set_linker_script(mbed-mimxrt1170-evk ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/CMakeLists.txt

@@ -0,0 +1,26 @@
+# Copyright (c) 2021 ARM Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+add_library(mbed-evk INTERFACE)
+
+target_include_directories(mbed-evk
+    INTERFACE
+        .
+        xip
+)
+
+target_sources(mbed-evk
+    INTERFACE
+        analogin_api.c
+        flash_api.c
+        clock_config.c
+        mbed_overrides.c
+        PeripheralPins.c
+        pinmap.c
+        serial_api.c
+        us_ticker.c
+
+
+        xip/evkmimxrt1170_flexspi_nor_config.c
+        xip/dcd.c
+)

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/PeripheralNames.h

@@ -0,0 +1,142 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    OSC32KCLK = 0,
+} RTCName;
+
+typedef enum {
+    UART_1 = 1,
+    UART_2 = 2,
+    UART_3 = 3,
+    UART_4 = 4,
+} UARTName;
+
+#define STDIO_UART_TX     USBTX
+#define STDIO_UART_RX     USBRX
+#define STDIO_UART        UART_1
+
+#define SION_BIT_SHIFT        (3)
+#define DAISY_REG_SHIFT       (4)
+#define DAISY_REG_VALUE_SHIFT (16)
+
+typedef enum {
+    I2C_1 = 1,
+    I2C_2 = 2,
+    I2C_3 = 3,
+    I2C_4 = 4,
+    I2C_5 = 5,
+} I2CName;
+
+#define PWM_MODULE_SHIFT   2
+#define PWM_SHIFT          8
+
+typedef enum {
+    PWM_1  = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0),  // PWM1 Submodule 0 PWMA
+    PWM_2  = (1 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1),  // PWM1 Submodule 0 PWMB
+    PWM_3  = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0),  // PWM1 Submodule 1 PWMA
+    PWM_4  = (1 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1),  // PWM1 Submodule 1 PWMB
+    PWM_5  = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0),  // PWM1 Submodule 2 PWMA
+    PWM_6  = (1 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1),  // PWM1 Submodule 2 PWMB
+    PWM_7  = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0),  // PWM1 Submodule 3 PWMA
+    PWM_8  = (1 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1),  // PWM1 Submodule 3 PWMB
+    PWM_9  = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0),  // PWM2 Submodule 0 PWMA
+    PWM_10 = (2 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1),  // PWM2 Submodule 0 PWMB
+    PWM_11 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0),  // PWM2 Submodule 1 PWMA
+    PWM_12 = (2 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1),  // PWM2 Submodule 1 PWMB
+    PWM_13 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0),  // PWM2 Submodule 2 PWMA
+    PWM_14 = (2 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1),  // PWM2 Submodule 2 PWMB
+    PWM_15 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0),  // PWM2 Submodule 3 PWMA
+    PWM_16 = (2 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1),  // PWM2 Submodule 3 PWMB
+    PWM_17 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0),  // PWM3 Submodule 0 PWMA
+    PWM_18 = (3 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1),  // PWM3 Submodule 0 PWMB
+    PWM_19 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0),  // PWM3 Submodule 1 PWMA
+    PWM_20 = (3 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1),  // PWM3 Submodule 1 PWMB
+    PWM_21 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0),  // PWM3 Submodule 2 PWMA
+    PWM_22 = (3 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1),  // PWM3 Submodule 2 PWMB
+    PWM_23 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0),  // PWM3 Submodule 3 PWMA
+    PWM_24 = (3 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1),  // PWM3 Submodule 3 PWMB
+    PWM_25 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (0),  // PWM4 Submodule 0 PWMA
+    PWM_26 = (4 << PWM_SHIFT) | (0 << PWM_MODULE_SHIFT) | (1),  // PWM4 Submodule 0 PWMB
+    PWM_27 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (0),  // PWM4 Submodule 1 PWMA
+    PWM_28 = (4 << PWM_SHIFT) | (1 << PWM_MODULE_SHIFT) | (1),  // PWM4 Submodule 1 PWMB
+    PWM_29 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (0),  // PWM4 Submodule 2 PWMA
+    PWM_30 = (4 << PWM_SHIFT) | (2 << PWM_MODULE_SHIFT) | (1),  // PWM4 Submodule 2 PWMB
+    PWM_31 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (0),  // PWM4 Submodule 3 PWMA
+    PWM_32 = (4 << PWM_SHIFT) | (3 << PWM_MODULE_SHIFT) | (1)   // PWM4 Submodule 3 PWMB
+} PWMName;
+
+#define ADC_INSTANCE_SHIFT           8
+typedef enum {
+    ADC1_0 = (1 << ADC_INSTANCE_SHIFT | 0),
+    ADC1_1 = (1 << ADC_INSTANCE_SHIFT | 1),
+    ADC1_2 = (1 << ADC_INSTANCE_SHIFT | 2),
+    ADC1_3 = (1 << ADC_INSTANCE_SHIFT | 3),
+    ADC1_4 = (1 << ADC_INSTANCE_SHIFT | 4),
+    ADC1_5 = (1 << ADC_INSTANCE_SHIFT | 5),
+    ADC1_6 = (1 << ADC_INSTANCE_SHIFT | 6),
+    ADC1_7 = (1 << ADC_INSTANCE_SHIFT | 7),
+    ADC1_8 = (1 << ADC_INSTANCE_SHIFT | 8),
+    ADC1_9 = (1 << ADC_INSTANCE_SHIFT | 9),
+    ADC1_10 = (1 << ADC_INSTANCE_SHIFT | 10),
+    ADC1_11 = (1 << ADC_INSTANCE_SHIFT | 11),
+    ADC1_12 = (1 << ADC_INSTANCE_SHIFT | 12),
+    ADC1_13 = (1 << ADC_INSTANCE_SHIFT | 13),
+    ADC1_14 = (1 << ADC_INSTANCE_SHIFT | 14),
+    ADC1_15 = (1 << ADC_INSTANCE_SHIFT | 15),
+    ADC2_0 = (2 << ADC_INSTANCE_SHIFT | 0),
+    ADC2_1 = (2 << ADC_INSTANCE_SHIFT | 1),
+    ADC2_2 = (2 << ADC_INSTANCE_SHIFT | 2),
+    ADC2_3 = (2 << ADC_INSTANCE_SHIFT | 3),
+    ADC2_4 = (2 << ADC_INSTANCE_SHIFT | 4),
+    ADC2_5 = (2 << ADC_INSTANCE_SHIFT | 5),
+    ADC2_6 = (2 << ADC_INSTANCE_SHIFT | 6),
+    ADC2_7 = (2 << ADC_INSTANCE_SHIFT | 7),
+    ADC2_8 = (2 << ADC_INSTANCE_SHIFT | 8),
+    ADC2_9 = (2 << ADC_INSTANCE_SHIFT | 9),
+    ADC2_10 = (2 << ADC_INSTANCE_SHIFT | 10),
+    ADC2_11 = (2 << ADC_INSTANCE_SHIFT | 11),
+    ADC2_12 = (2 << ADC_INSTANCE_SHIFT | 12),
+    ADC2_13 = (2 << ADC_INSTANCE_SHIFT | 13),
+    ADC2_14 = (2 << ADC_INSTANCE_SHIFT | 14),
+    ADC2_15 = (2 << ADC_INSTANCE_SHIFT | 15),
+} ADCName;
+
+typedef enum {
+    DAC_0 = 0
+} DACName;
+
+
+typedef enum {
+    SPI_1 = 1,
+    SPI_2 = 2,
+    SPI_3 = 3,
+} SPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/PeripheralPins.c

@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "PeripheralPins.h"
+
+/************RTC***************/
+const PinMap PinMap_RTC[] = {
+    {NC, OSC32KCLK, 0},
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {GPIO_AD_10, ADC1_0, NC},
+    {GPIO_AD_11, ADC1_1, NC},
+    {GPIO_AD_12, ADC1_2, NC},
+    {GPIO_AD_13, ADC1_3, NC},
+    {GPIO_AD_09, ADC1_4, NC},
+    {GPIO_AD_08, ADC1_5, NC},
+    {NC   , NC       , 0}
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {NC      , NC   , 0}
+};
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+   {GPIO_LPSR_04   , I2C_5   , 0},
+   {NC   , NC   , 0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+   {GPIO_LPSR_05   , I2C_5   , 0},
+   {NC   , NC   , 0}
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    {GPIO_AD_24, UART_1, 0},
+    {GPIO_DISP_B2_10, UART_2, 2},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {GPIO_AD_25, UART_1, 0},
+    {GPIO_DISP_B2_11, UART_2, 2},
+    {NC   , NC   , 0}
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    {GPIO_AD_28  , SPI_1   , 0},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {GPIO_AD_30   , SPI_1   , 0},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {GPIO_AD_31   , SPI_1   , 0},
+    {NC   , NC   , 0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {GPIO_AD_29  , SPI_1   , 0},
+    {NC   , NC   , 0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {NC   , NC    , 0}
+};
+