Nuvoton: Enable no HXT/LXT configurability

targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h

@@ -50,7 +50,11 @@ extern "C" {
 #define __HSI       (48000000UL)              /*!< PLL default output is 48MHz */
 #define __SYS_OSC_CLK     (    ___HSI)        /*!< Main oscillator frequency */
 
+#if MBED_CONF_TARGET_HXT_PRESENT
 #define __SYSTEM_CLOCK    (1UL*__HXT)
+#else
+#define __SYSTEM_CLOCK    (1UL*__HIRC)
+#endif
 
 extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
 extern uint32_t CyclesPerUs;        /*!< Cycles per micro second              */

targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c

@@ -31,7 +31,11 @@
 /* Timer clock per lp_ticker tick */
 #define NU_TMRCLK_PER_TICK          1
 /* Timer clock per second */
+#if MBED_CONF_TARGET_LXT_PRESENT
 #define NU_TMRCLK_PER_SEC           (__LXT)
+#else
+#define NU_TMRCLK_PER_SEC           (__LIRC)
+#endif
 /* Timer max counter bit size */
 #define NU_TMR_MAXCNT_BITSIZE       24
 /* Timer max counter */
@@ -40,7 +44,11 @@
 static void tmr1_vec(void);
 
 /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+#if MBED_CONF_TARGET_LXT_PRESENT
 static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#else
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#endif
 
 #define TIMER_MODINIT       timer1_modinit
 

targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c

@@ -33,47 +33,61 @@ void mbed_sdk_init(void)
     /* Unlock protected registers */
     SYS_UnlockReg();
 
-#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* HXT Enable: Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
     PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
 #endif
 
+#if MBED_CONF_TARGET_LXT_PRESENT
     /* LXT Enable: Set X32_OUT(PF.4) and X32_IN(PF.5) to input mode */
     PF->MODE &= ~(GPIO_MODE_MODE4_Msk | GPIO_MODE_MODE5_Msk);
+#endif
 
     /* Enable HIRC clock (Internal RC 48MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
-#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Enable HXT clock (external XTAL 12MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+#else
+    /* Disable HXT clock (external XTAL 12MHz) */
+    CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
 #endif
-    /* Enable LIRC for lp_ticker */
+    /* Enable LIRC */
     CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
-    /* Enable LXT for RTC */
+#if MBED_CONF_TARGET_LXT_PRESENT
+    /* Enable LXT */
     CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+#else
+    /* Disable LXT */
+    CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+#endif
 
     /* Wait for HIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
-#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Wait for HXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
 #endif
     /* Wait for LIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+#if MBED_CONF_TARGET_LXT_PRESENT
     /* Wait for LXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+#endif
 
-#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL)
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* HXT Enable: Disable digital input path of analog pin XT1_OUT to prevent leakage */
     GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 2));
     /* HXT Enable: Disable digital input path of analog pin XT1_IN to prevent leakage */
     GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 3));
 #endif
 
+#if MBED_CONF_TARGET_LXT_PRESENT
     /* LXT Enable: Disable digital input path of analog pin X32_OUT to prevent leakage */
     GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 4));
     /* LXT Enable: Disable digital input path of analog pin XT32_IN to prevent leakage */
     GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 5));
+#endif
 
     /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
     CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));

targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c

@@ -26,6 +26,14 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
+/* Not support LIRC-clocked RTC
+ *
+ * H/W doesn't support this path.
+ */
+#if !MBED_CONF_TARGET_LXT_PRESENT
+#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json"
+#endif
+
 /* Micro seconds per second */
 #define NU_US_PER_SEC               1000000
 /* Timer clock per second

targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c

@@ -30,7 +30,11 @@
 /* Timer clock per lp_ticker tick */
 #define NU_TMRCLK_PER_TICK          1
 /* Timer clock per second */
+#if MBED_CONF_TARGET_LXT_PRESENT
 #define NU_TMRCLK_PER_SEC           (__LXT)
+#else
+#define NU_TMRCLK_PER_SEC           (__LIRC)
+#endif
 /* Timer max counter bit size */
 #define NU_TMR_MAXCNT_BITSIZE       24
 /* Timer max counter */
@@ -40,7 +44,11 @@
 static void tmr1_vec(void);
 
 /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+#if MBED_CONF_TARGET_LXT_PRESENT
 static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#else
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#endif
 
 #define TIMER_MODINIT       timer1_modinit
 

targets/TARGET_NUVOTON/TARGET_M261/mbed_overrides.c

@@ -36,23 +36,37 @@ void mbed_sdk_init(void)
 
     /* Enable HIRC clock (Internal RC 12MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Enable HXT clock (external XTAL 12MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
-    /* Enable LIRC for lp_ticker */
+#else
+    /* Disable HXT clock (external XTAL 12MHz) */
+    CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+#endif
+    /* Enable LIRC */
     CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
-    /* Enable LXT for RTC */
+#if MBED_CONF_TARGET_LXT_PRESENT
+    /* Enable LXT */
     CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+#else
+    /* Disable LXT */
+    CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+#endif
     /* Enable HIRC48 clock (Internal RC 48MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk);
 
     /* Wait for HIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Wait for HXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+#endif
     /* Wait for LIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+#if MBED_CONF_TARGET_LXT_PRESENT
     /* Wait for LXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+#endif
     /* Wait for HIRC48 clock ready */
     CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk);
 

targets/TARGET_NUVOTON/TARGET_M261/rtc_api.c

@@ -25,13 +25,27 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
+/* Not support LIRC-clocked RTC
+ *
+ * Though H/W supports this path, it is still not supported because:
+ * 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates.
+ * 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing.
+ */
+#if !MBED_CONF_TARGET_LXT_PRESENT
+#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json"
+#endif
+
 /* Micro seconds per second */
 #define NU_US_PER_SEC               1000000
 /* Timer clock per second
  *
  * NOTE: This dependents on real hardware.
  */
+#if MBED_CONF_TARGET_LXT_PRESENT
 #define NU_RTCCLK_PER_SEC           __LXT
+#else
+#define NU_RTCCLK_PER_SEC           __LIRC
+#endif
 
 /* Strategy for implementation of RTC HAL
  *
@@ -85,7 +99,11 @@ static time_t t_write = 0;
 /* Convert date time from H/W RTC to struct TM */
 static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
 
+#if MBED_CONF_TARGET_LXT_PRESENT
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL};
+#else
+static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL};
+#endif
 
 void rtc_init(void)
 {

targets/TARGET_NUVOTON/TARGET_M261/trng_api.cpp

@@ -48,6 +48,25 @@ void trng_init(MBED_UNUSED trng_t *obj)
         /* Reset IP */
         SYS_ResetModule(trng_modinit.rsetidx);
 
+#if MBED_CONF_TARGET_LXT_PRESENT
+        /* 32K clock from (external) LXT */
+#else
+        /* 32K clock from LIRC32 */
+
+        /* Unlock protected registers */
+        SYS_UnlockReg();
+
+        /* To access RTC registers, clock must be enabled first. */
+        CLK_EnableModuleClock(RTC_MODULE);
+
+        /* Enable 32K clock from LIRC32 */
+        RTC->LXTCTL |= (RTC_LXTCTL_C32KS_Msk | RTC_LXTCTL_LIRC32KEN_Msk);
+        CLK_WaitClockReady(CLK_STATUS_LIRC32STB_Msk | CLK_STATUS_LXTSTB_Msk);
+
+        /* Lock protected registers */
+        SYS_LockReg();
+#endif
+
         TRNG_T *trng_base = (TRNG_T *) NU_MODBASE(trng_modinit.modname);
 
         trng_base->ACT |= TRNG_ACT_ACT_Msk;

targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c

@@ -265,10 +265,12 @@ void Reset_Handler(void)
 
     /* Disable Power-on Reset function */
     SYS_DISABLE_POR();
-
+
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* HXT Crystal Type Select: INV */
     CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
-
+#endif
+
     /**
      * NOTE 1: Unlock is required for perhaps some register access in SystemInit().
      * NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start.

targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c

@@ -84,8 +84,10 @@ void SystemInit(void)
     {
         M32(GCR_BASE+0x14) |= BIT7;
     }
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Force to use INV type with HXT */
     CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk;
+#endif
     SYS_LockReg();
 
 

targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h

@@ -38,7 +38,11 @@ extern "C" {
 #define __SYS_OSC_CLK     (    ___HSI)    /* Main oscillator frequency        */
 
 
+#if MBED_CONF_TARGET_HXT_PRESENT
 #define __SYSTEM_CLOCK    (1*__HXT)
+#else
+#define __SYSTEM_CLOCK    (1*__HIRC)
+#endif
 
 extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
 extern uint32_t CyclesPerUs;         /*!< Cycles per micro second              */

targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c

@@ -29,7 +29,11 @@
 /* Timer clock per lp_ticker tick */
 #define NU_TMRCLK_PER_TICK          1
 /* Timer clock per second */
+#if MBED_CONF_TARGET_LXT_PRESENT
 #define NU_TMRCLK_PER_SEC           (__LXT)
+#else
+#define NU_TMRCLK_PER_SEC           (__LIRC)
+#endif
 /* Timer max counter bit size */
 #define NU_TMR_MAXCNT_BITSIZE       24
 /* Timer max counter */
@@ -38,7 +42,11 @@
 static void tmr1_vec(void);
 
 /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+#if MBED_CONF_TARGET_LXT_PRESENT
 static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#else
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#endif
 
 #define TIMER_MODINIT      timer1_modinit
 

targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c

@@ -33,21 +33,35 @@ void mbed_sdk_init(void)
 
     /* Enable HIRC clock (Internal RC 22.1184MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Enable HXT clock (external XTAL 12MHz) */
     CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
-    /* Enable LIRC for lp_ticker */
+#else
+    /* Disable HXT clock (external XTAL 12MHz) */
+    CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+#endif
+    /* Enable LIRC */
     CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
-    /* Enable LXT for RTC */
+#if MBED_CONF_TARGET_LXT_PRESENT
+    /* Enable LXT */
     CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+#else
+    /* Disable LXT */
+    CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk);
+#endif
 
     /* Wait for HIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+#if MBED_CONF_TARGET_HXT_PRESENT
     /* Wait for HXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+#endif
     /* Wait for LIRC clock ready */
     CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+#if MBED_CONF_TARGET_LXT_PRESENT
     /* Wait for LXT clock ready */
     CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+#endif
 
     /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
     CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));

targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c

@@ -24,13 +24,27 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
+/* Not support LIRC-clocked RTC
+ *
+ * Though H/W supports this path, it is still not supported because:
+ * 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates.
+ * 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing.
+ */
+#if !MBED_CONF_TARGET_LXT_PRESENT
+#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json"
+#endif
+
 /* Micro seconds per second */
 #define NU_US_PER_SEC               1000000
 /* Timer clock per second
  *
  * NOTE: This dependents on real hardware.
  */
+#if MBED_CONF_TARGET_LXT_PRESENT
 #define NU_RTCCLK_PER_SEC           __LXT
+#else
+#define NU_RTCCLK_PER_SEC           __LIRC
+#endif
 
 /* Strategy for implementation of RTC HAL
  *
@@ -84,7 +98,11 @@ static time_t t_write = 0;
 /* Convert date time from H/W RTC to struct TM */
 static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
 
+#if MBED_CONF_TARGET_LXT_PRESENT
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL};
+#else
+static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL};
+#endif
 
 void rtc_init(void)
 {