[Silicon Labs] Add support for the new EFM32 Pearl Gecko #1501
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Leopard Gecko used as baseline. TODO - Peripheral/GPIO pin mappings etc for Pearl are marked "Pearl ok", rest are wrong - Missing new (4.1.0+) emlib
New version with support for Pearl & co.
PWM pin mappings. Since the pins can be freely chosen (unlike in previous HW), there should be no need to use the other channels. Also corrected frequency for HFXO in ref devices.
Pearl GPIO block does not support DOUTSET/DOUTCLR, so use read+DOUTTGL instead.
Use RTCC API for lp_ticker on Pearl. Basic adaptation, but more work is required. Now frees RTC when ticker is not used (detected through interrupt disable), so that sleep modes below EM2 do not remain permanently blocked.
Removed DAC/AnalogOut, I2C1, UART0/1, LEUART1, USART2, GPIO Drive support and GPIO port E.
ADC pinmap updated, PinMap_DAC removed, since DEVICE_ANALOGOUT not supported
Mbed needs to have interrupt vectors in RAM so reserve space at the beginning of memory, and export the relevant symbols.
Normal UARTs not present, use USART.
Use new ROUTEPEN/ROUTELOC0 registers for selecting I2C pins.
Conditionals for including em_rtc.h and em_rtcc.h. Use the correct interrupt name in RTCC code.
LDMA support for the dma_api module
analogin_api.c changed to make it compile. Compilation error will be generated if _ADC_SINGLECTRL_POSSEL_MASK || _ADC_SINGLECTRL_INPUTSEL_MASK is not defined. This is because NEGATIVE voltage measurement is not supported by MBED API.
Serial pin routing for Pearl. Note that this currently requires the pins to be in the same "location", even though this is not needed by the Pearl HW.
LDMA support for serial HAL. Adds callback support for emlib LDMA code so that most of the old serial code can be reused. Note: Serial shows some signs of life on the bus, but DMA mode is completely untested.
Channel selection shifted to right place. Now It seems to work at least with channel PC11. Weird thing is, that floating pin gives result 0.4. Should be 0.0.
Any channel can be used. It is possible to have 4 pwm outputs active at a same time, if PinMap_PWM configuration is done properly. Future improvement proposal: dynamic channel selection!
LDMA now functional for both RX/TX. One hack remains - need to check if TXC interrupt check can be removed from older platforms, or if flagging is necessary.
GPIO pins were uninitialized. Fixed and tested.
Correct routing for SPI pins on Pearl
SPI dma forced to compile. Continuing improvements...
Number of interrupt slots reported by different files before this commit:
giant happy leopard pearl wonder zero
spec 39 21 39 34 39 17
nvic 39 21 39 34 40 19
startup.s 39 21 40 34 40 19
gcc link 40 21 41 34 40 19
arm link 40 22 40 - 40 16
reserved 0 0 1 0 0 2
spec - reference manual
nvic.h - cmsis_nvic.h
startup.s - assembler startup files
gcc link - efm32*.ld linker script for GCC
arm link - efm32*.sct linker script for ARM (RVCT)
reserved - number of 'reserved' slots at the end of irq table in startup.s files
Fixed amounts to reflect those in the startup files, including reserved
slots:
Giant
Reduce amount in GCC and ARM linker files to 39
Happy
Fix comment in GCC linker file
Reduce amount in ARM linker file to 21
Leopard
Increase amount to 40 in cmsis_nvic.h
Reduce amount to 40 in GCC linker file (this bug caused by
emlib 4.1.0 port commit 1923e8b4)
Wonder
No changes, but note that ref. manual does not list FPUEH
interrupt that is included in startup files at index 39
Zero
Increase amount to 19 in ARM linker file
Read as not returning correct values, because RTCC (or RTC in other Gecko's) was not initiated. This was a problem in every Gecko. If RTCC is initiated for lptimer it is done without binding it to irqhandler (since irq not needed). Also implementation for geckos using RTC added. Tested with pearl and happy geckos
…ger part of the API.
* Added PD9 back in (for some reason it was at some point removed from the pinmap, not sure why because it is a usable pin when you remove the on-board sensor or use the Pearl chip standalone) * Fixed PWM locations to match the pin-CC channel combinations.
* Setting the PWM period now correctly updates all other channels to keep their duty cycle * No longer keep values in RAM that can be read directly from a register * Setting the PWM duty cycle to 100% no longer makes the signal glitch on every period * Code condensation
…ansfer means the transaction is finished already, and its handling is thus less time-sensitive than being in the middle of an interrupt-driven Serial or SPI transaction.
…and remove said code.
Emlib should now match the standard SiLabs release. Required extensions have been moved to dma_api and marked with LDMAx_ prefix.
…the RAM layout w.r.t. alignment.
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Please share the test output from singletest.py |
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Test summary: Completed in 1943.09 sec |
* Allow pins to be configured as NC without failing or asserting * Fix putc() to not return before the entire character has been physically shifted out. * Use MBED_ASSERT * Fix baudrate calculation to avoid wrong configuration on startup for stdio
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Was a bit too quick on the trigger for the test report... Test report is after the last commits have been applied. |
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+1 |
[Silicon Labs] Add support for the new EFM32 Pearl Gecko
Rebased & opened a new pull request.
New release of the Silicon Labs HAL for mbed.
Changelog: