mBed and nrf-mbed merge

libraries/mbed/common/rtc_time.c

@@ -19,11 +19,15 @@
 #include "rtc_time.h"
 #include "us_ticker_api.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif 
 #if defined (__ICCARM__)
 time_t __time32(time_t *timer)
 #else
 time_t time(time_t *timer)
 #endif
+
 {
 #if DEVICE_RTC
     if (!(rtc_isenabled())) {
@@ -53,3 +57,7 @@ clock_t clock() {
     t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
     return t;
 }
+
+#ifdef __cplusplus
+}
+#endif 

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/TOOLCHAIN_ARM_STD/nRF51822.sct

@@ -0,0 +1,27 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000  {    
+;  ER_IROM1 0x00000000 0x00040000  {  
+;   *.o (RESET, +First)
+;   *(InRoot$$Sections)
+;   .ANY (+RO)
+;  }
+;  RW_IRAM1 0x20000000 0x00004000  { 
+;   .ANY (+RW +ZI)
+;  }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x14000 0x002C000  {    
+  ER_IROM1 0x14000 0x002C000  {  
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20002000 0x00002000  { 
+   .ANY (+RW +ZI)
+  }
+}
+
+
+

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/TOOLCHAIN_ARM_STD/startup_nRF51822.s

@@ -0,0 +1,187 @@
+; mbed Microcontroller Library
+; Copyright (c) 2006-2013 ARM Limited
+;Licensed under the Apache License, Version 2.0 (the "License");
+;you may not use this file except in compliance with the License.
+;You may obtain a copy of the License at
+;http://www.apache.org/licenses/LICENSE-2.0
+;Unless required by applicable law or agreed to in writing, software
+;distributed under the License is distributed on an "AS IS" BASIS,
+;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;See the License for the specific language governing permissions and
+;limitations under the License.
+
+; Description message
+
+__initial_sp	EQU     0x20004000
+
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+                DCD      RADIO_IRQHandler ;RADIO
+                DCD      UART0_IRQHandler ;UART0
+                DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+                DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+                DCD      0 ;Reserved
+                DCD      GPIOTE_IRQHandler ;GPIOTE
+                DCD      ADC_IRQHandler ;ADC
+                DCD      TIMER0_IRQHandler ;TIMER0
+                DCD      TIMER1_IRQHandler ;TIMER1
+                DCD      TIMER2_IRQHandler ;TIMER2
+                DCD      RTC0_IRQHandler ;RTC0
+                DCD      TEMP_IRQHandler ;TEMP
+                DCD      RNG_IRQHandler ;RNG
+                DCD      ECB_IRQHandler ;ECB
+                DCD      CCM_AAR_IRQHandler ;CCM_AAR
+                DCD      WDT_IRQHandler ;WDT
+                DCD      RTC1_IRQHandler ;RTC1
+                DCD      QDEC_IRQHandler ;QDEC
+                DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+                DCD      SWI0_IRQHandler ;SWI0
+                DCD      SWI1_IRQHandler ;SWI1
+                DCD      SWI2_IRQHandler ;SWI2
+                DCD      SWI3_IRQHandler ;SWI3
+                DCD      SWI4_IRQHandler ;SWI4
+                DCD      SWI5_IRQHandler ;SWI5
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+NRF_POWER_RAMON_ADDRESS           EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU   0xF         ; All RAM blocks on in onmode bit mask
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit				
+                IMPORT  __main
+                LDR     R0, =NRF_POWER_RAMON_ADDRESS
+                LDR     R2, [R0]
+                MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+                ORRS    R2, R2, R1
+                STR     R2, [R0]
+                LDR     R0, =SystemInit               
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   POWER_CLOCK_IRQHandler [WEAK]
+                EXPORT   RADIO_IRQHandler [WEAK]
+                EXPORT   UART0_IRQHandler [WEAK]
+                EXPORT   SPI0_TWI0_IRQHandler [WEAK]
+                EXPORT   SPI1_TWI1_IRQHandler [WEAK]
+                EXPORT   GPIOTE_IRQHandler [WEAK]
+                EXPORT   ADC_IRQHandler [WEAK]
+                EXPORT   TIMER0_IRQHandler [WEAK]
+                EXPORT   TIMER1_IRQHandler [WEAK]
+                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   RTC0_IRQHandler [WEAK]
+                EXPORT   TEMP_IRQHandler [WEAK]
+                EXPORT   RNG_IRQHandler [WEAK]
+                EXPORT   ECB_IRQHandler [WEAK]
+                EXPORT   CCM_AAR_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler [WEAK]
+                EXPORT   RTC1_IRQHandler [WEAK]
+                EXPORT   QDEC_IRQHandler [WEAK]
+                EXPORT   LPCOMP_COMP_IRQHandler [WEAK]
+                EXPORT   SWI0_IRQHandler [WEAK]
+                EXPORT   SWI1_IRQHandler [WEAK]
+                EXPORT   SWI2_IRQHandler [WEAK]
+                EXPORT   SWI3_IRQHandler [WEAK]
+                EXPORT   SWI4_IRQHandler [WEAK]
+                EXPORT   SWI5_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UART0_IRQHandler
+SPI0_TWI0_IRQHandler
+SPI1_TWI1_IRQHandler
+GPIOTE_IRQHandler
+ADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+LPCOMP_COMP_IRQHandler
+SWI0_IRQHandler
+SWI1_IRQHandler
+SWI2_IRQHandler
+SWI3_IRQHandler
+SWI4_IRQHandler
+SWI5_IRQHandler
+
+                B .
+                ENDP
+                ALIGN
+                END
+

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/TOOLCHAIN_ARM_STD/sys.cpp

@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/cmsis.h

@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * A generic CMSIS include header, pulling in LPC407x_8x specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "nrf51822.h"
+#include "cmsis_nvic.h"
+
+#endif

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/cmsis_nvic.c

@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library - cmsis_nvic for LCP407x_8x
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+#include "cmsis_nvic.h"
+
+/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
+ * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), 
+ * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF 
+ * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
+ * 
+ * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
+ * above the vector table before 0x200 will actually go to RAM. So we need to provide 
+ * a solution where the compiler gets the right results based on the memory map
+ *
+ * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
+ *  - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
+ *  - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
+ * 
+ * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there  
+ *  - No flash accesses will go to ram, as there will be nothing there
+ *  - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
+ *  - RAM overhead: 0, FLASH overhead: 320 bytes
+ *
+ * Option 2 is the one to go for, as RAM is the most valuable resource
+ */
+
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+/*
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}*/
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    int i;
+    // Space for dynamic vectors, initialised to allocate in R/W
+    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+    /*
+    // Copy and switch to dynamic vectors if first time called
+    if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {     
+      uint32_t *old_vectors = (uint32_t *)0;         // FLASH vectors are at 0x0
+      for(i = 0; i < NVIC_NUM_VECTORS; i++) {    
+            vectors[i] = old_vectors[i];
+        }
+        LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
+    }*/
+
+    // Set the vector 
+    vectors[IRQn + 16] = vector; 
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    // We can always read vectors at 0x0, as the addresses are remapped
+    uint32_t *vectors = (uint32_t*)0; 
+
+    // Return the vector
+    return vectors[IRQn + 16];
+}

libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_NRF51822/cmsis_nvic.h

@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */ 
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS      (16 + 32)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "nrf51822.h"
+#include "cmsis.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif