ncs36510 from ON Semiconductor

hal/targets.json

@@ -2009,5 +2009,17 @@
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "features": ["IPV4"],
         "release_versions": ["2", "5"]
+    },    
+    "NCS36510": {
+        "inherits": ["Target"],
+        "core": "Cortex-M3",
+        "extra_labels": ["ONSEMI"],
+        "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
+        "macros": ["REVD", "CM3", "CPU_NCS36510", "TARGET_NCS36510"],
+        "progen": {"target": "ncs36510"},
+        "progen_target": "ncs36510",
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI"],
+        "release_versions": ["2", "5"]
     }
 }

hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/NCS36510.h

@@ -0,0 +1,92 @@
+/**************************************************************************/
+/**
+ * @file     ARMCM3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ *           for CM3 Device Series
+ * @version  V1.05
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef ARMCM3_H
+#define ARMCM3_H
+
+/**
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+	/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
+	NonMaskableInt_IRQn 	= -14, 		/*!<  2 Cortex-M3 Non Maskable Interrupt                  */
+	HardFault_IRQn 			= -13, 		/*!<  3 Cortex-M3 Hard Fault Interrupt                    */
+	MemoryManagement_IRQn 	= -12, 		/*!<  4 Cortex-M3 Memory Management Interrupt             */
+	BusFault_IRQn 			= -11,		/*!<  5 Cortex-M3 Bus Fault Interrupt                     */
+	UsageFault_IRQn 		= -10, 		/*!<  6 Cortex-M3 Usage Fault Interrupt                   */
+	SVCall_IRQn 			= -5, 		/*!< 11 Cortex-M3 SV Call Interrupt                       */
+	DebugMonitor_IRQn 		= -4, 		/*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+	PendSV_IRQn 			= -2, 		/*!< 14 Cortex-M3 Pend SV Interrupt                       */
+	SysTick_IRQn			= -1, 		/*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+	/******  ARMCM3 specific Interrupt Numbers ********************************************************/
+	Tim0_IRQn 				= 0,
+	Tim1_IRQn 				= 1,
+	Tim2_IRQn 				= 2,
+	Uart1_IRQn 				= 3,
+	Spi_IRQn 				= 4,
+	I2C_IRQn 				= 5,
+	Gpio_IRQn 				= 6,
+	Rtc_IRQn 				= 7,
+	Flash_IRQn 				= 8,
+	MacHw_IRQn 				= 9,
+	Aes_IRQn 				= 10,
+	Adc_IRQn 				= 11,
+	ClockCal_IRQn 			= 12,
+	Uart2_IRQn 				= 13,
+	Uvi_IRQn				= 14,
+	Dma_IRQn 				= 15,
+	DbgPwrUp_IRQn 			= 16,
+	Spi2_IRQn 				= 17,
+	I2C2_IRQn 				= 18,
+	FVDDHComp_IRQn			= 19
+} IRQn_Type;
+
+/**
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/** Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __CM3_REV                 0x0201    /*!< Core Revision r2p1                               */
+#define __MPU_PRESENT             1         /*!< MPU present or not                               */
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
+
+//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET	16
+//#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER	20
+//#define NVIC_NUM_VECTORS     (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
+
+//#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
+//#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS	0x3000
+
+#include <core_cm3.h>                       /* Cortex-M3 processor and core peripherals           */
+#include "system_NCS36510.h"                  /* System Header                                      */
+
+#endif  /* ARMCM3_H */

hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/TOOLCHAIN_ARM/NCS36510.sct

@@ -0,0 +1,23 @@
+#! armcc -E
+
+#define Heap_Size                    0x0400
+
+LR_IROM1 0x00003000 0x0004F000  {    ; load region size_region
+  ER_IROM1 0x00003000 0x0004F000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (*)
+  }
+
+  ; no uvisor support at this time
+
+  ;ARM_LIB_STACK AlignExpr(+0, 8) EMPTY 0x1000 {}
+   ARM_LIB_STACK 0x3FFF4000 EMPTY 0x1000 {}
+
+  RW_IRAM0 +0 {
+    .ANY(+RW +ZI)
+  }
+  RW_IRAM1 ImageLimit(RW_IRAM0) EMPTY Heap_Size { ; Heap region growing up
+  }
+  ARM_LIB_HEAP AlignExpr(+0, 8) ALIGN 8 EMPTY (0x3FFF4000 + 0xC000 - AlignExpr(ImageLimit(RW_IRAM1),8) ) {}
+}

hal/targets/cmsis/TARGET_ONSEMI/TARGET_NCS36510/TOOLCHAIN_ARM/startup_NCS36510.s

@@ -0,0 +1,208 @@
+;/* File: startup_ncs36510.s
+; * Purpose: startup file for Cortex-M3 devices. Should use with
+; *   ARMGCC for ARM Embedded Processors
+; * Version: V2.00
+; * Date: 25 Feb 2016
+; *
+; */
+;/* Copyright (c) 2011 - 2014 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0x3000 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit|  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     HardFault_Handler  ; Hard Fault Handler
+                DCD     MemManage_Handler  ; MPU Fault Handler
+                DCD     BusFault_Handler  ; Bus Fault Handler
+                DCD     UsageFault_Handler  ; Usage Fault Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     DebugMon_Handler  ; Debug Monitor Handler
+                DCD     0  ; Reserved
+                DCD     PendSV_Handler  ; PendSV Handler
+                DCD     SysTick_Handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     fIrqTim0Handler
+              	DCD     fIrqTim1Handler
+              	DCD     fIrqTim2Handler
+              	DCD     fIrqUart1Handler
+              	DCD     fIrqSpiHandler
+              	DCD     fIrqI2CHandler
+              	DCD     fIrqGpioHandler
+              	DCD     fIrqRtcHandler
+              	DCD     fIrqFlashHandler
+              	DCD     fIrqMacHwHandler
+              	DCD     fIrqAesHandler
+              	DCD     fIrqAdcHandler
+              	DCD     fIrqClockCalHandler
+              	DCD     fIrqUart2Handler
+              	DCD     fIrqUviHandler
+              	DCD     fIrqDmaHandler
+               	DCD     fIrqDbgPwrUpHandler
+               	DCD     fIrqSpi2Handler
+               	DCD     fIrqI2C2Handler
+               	DCD     fIrqFVDDHCompHandler
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+              AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT      fIrqTim0Handler  [WEAK]
+                EXPORT      fIrqTim1Handler  [WEAK]
+                EXPORT      fIrqTim2Handler  [WEAK]
+                EXPORT      fIrqUart1Handler  [WEAK]
+                EXPORT      fIrqSpiHandler  [WEAK]
+                EXPORT      fIrqI2CHandler  [WEAK]
+                EXPORT      fIrqGpioHandler  [WEAK]
+                EXPORT      fIrqRtcHandler  [WEAK]
+                EXPORT      fIrqFlashHandler  [WEAK]
+                EXPORT      fIrqMacHwHandler  [WEAK]
+                EXPORT      fIrqAesHandler  [WEAK]
+                EXPORT      fIrqAdcHandler  [WEAK]
+                EXPORT      fIrqClockCalHandler  [WEAK]
+                EXPORT      fIrqUart2Handler  [WEAK]
+                EXPORT      fIrqUviHandler  [WEAK]
+                EXPORT      fIrqDmaHandler  [WEAK]
+                EXPORT      fIrqDbgPwrUpHandler  [WEAK]
+                EXPORT      fIrqSpi2Handler  [WEAK]
+                EXPORT      fIrqI2C2Handler  [WEAK]
+                EXPORT      fIrqFVDDHCompHandler  [WEAK]
+
+fIrqTim0Handler
+fIrqTim1Handler
+fIrqTim2Handler
+fIrqUart1Handler
+fIrqSpiHandler
+fIrqI2CHandler
+fIrqGpioHandler
+fIrqRtcHandler
+fIrqFlashHandler
+fIrqMacHwHandler
+fIrqAesHandler
+fIrqAdcHandler
+fIrqClockCalHandler
+fIrqUart2Handler
+fIrqUviHandler
+fIrqDmaHandler
+fIrqDbgPwrUpHandler
+fIrqSpi2Handler
+fIrqI2C2Handler
+fIrqFVDDHCompHandler
+DefaultISR
+
+                B       .
+
+                ENDP
+
+                EXPORT  __user_initial_stackheap
+                IMPORT  |Image$$ARM_LIB_HEAP$$Base|
+                IMPORT  |Image$$ARM_LIB_HEAP$$ZI$$Limit|
+
+__user_initial_stackheap PROC
+                LDR     R0, = |Image$$ARM_LIB_HEAP$$Base|
+                LDR     R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit|
+                BX      LR
+                ENDP
+
+                ALIGN
+                END