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[NUCLEO_F030R8/F302R8] Move back SetSysClock() call in SystemInit() #272

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Merged
merged 4 commits into from
Apr 23, 2014
Merged

[NUCLEO_F030R8/F302R8] Move back SetSysClock() call in SystemInit() #272

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3aa9e58
[NUCLEO_F030R8] Replace include of stm32f0xx.h with cmsis.h
bcostm Apr 22, 2014
6abba68
[NUCLEO_F302R8] Move back SetSysClock() call in SystemInit()
bcostm Apr 23, 2014
9daf443
[NUCLEO_F030R8] Move back SetSysClock() call in SystemInit()
bcostm Apr 23, 2014
b5d4979
[NUCLEO_F103RB] Many improvements
bcostm Apr 23, 2014
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4 changes: 4 additions & 0 deletions libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F030R8/system_stm32f0xx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -191,6 +191,10 @@ void SystemInit (void)

/* Disable all interrupts */
RCC->CIR = 0x00000000;

/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
}

/**
Expand Down
13 changes: 6 additions & 7 deletions libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c
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Expand Up @@ -147,8 +147,6 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}
* @{
*/

void SetSysClock(void);

#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
Expand Down Expand Up @@ -223,15 +221,15 @@ void SystemInit (void)
#endif /* DATA_IN_ExtSRAM */
#endif

/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();

#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
#endif

/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
SetSysClock();
}

/**
Expand Down Expand Up @@ -609,3 +607,4 @@ uint8_t SetSysClock_PLL_HSI(void)
*/

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2 changes: 2 additions & 0 deletions libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.h
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Expand Up @@ -93,6 +93,8 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc

extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);

/**
* @}
*/
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4 changes: 4 additions & 0 deletions libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/system_stm32f30x.c
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Expand Up @@ -212,6 +212,10 @@ void SystemInit(void)
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif

/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
}

/**
Expand Down
6 changes: 1 addition & 5 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F030R8/mbed_overrides.c
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Expand Up @@ -25,14 +25,10 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stm32f0xx.h"
#include "cmsis.h"

// This function is called after RAM initialization and before main.
void mbed_sdk_init() {
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();

// Update the SystemCoreClock variable.
SystemCoreClockUpdate();
}
7 changes: 4 additions & 3 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h
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Expand Up @@ -37,13 +37,13 @@ extern "C" {
#endif

typedef enum {
ADC_1 = (int)ADC1_BASE,
ADC_2 = (int)ADC2_BASE
ADC_1 = (int)ADC1_BASE
} ADCName;

typedef enum {
UART_1 = (int)USART1_BASE,
UART_2 = (int)USART2_BASE
UART_2 = (int)USART2_BASE,
UART_3 = (int)USART3_BASE
} UARTName;

#define STDIO_UART_TX PA_2
Expand All @@ -61,6 +61,7 @@ typedef enum {
} I2CName;

typedef enum {
PWM_1 = (int)TIM1_BASE,
PWM_2 = (int)TIM2_BASE,
PWM_3 = (int)TIM3_BASE,
PWM_4 = (int)TIM4_BASE
Expand Down
86 changes: 65 additions & 21 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c
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Expand Up @@ -35,12 +35,22 @@
#include "error.h"

static const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
{PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
{PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
{PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)},
{PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN0
{PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN1
{PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN2
{PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN3
{PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN4
{PA_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN5
{PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN6
{PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN7
{PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN8
{PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN9
{PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN10
{PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN11
{PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN12
{PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN13
{PC_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN14
{PC_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN15
{NC, NC, 0}
};

Expand All @@ -51,7 +61,7 @@ void analogin_init(analogin_t *obj, PinName pin) {
ADC_TypeDef *adc;
ADC_InitTypeDef ADC_InitStructure;

// Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object
// Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);

if (obj->adc == (ADCName)NC) {
Expand All @@ -71,17 +81,18 @@ void analogin_init(analogin_t *obj, PinName pin) {
// Get ADC registers structure address
adc = (ADC_TypeDef *)(obj->adc);

// Enable ADC clock
RCC_ADCCLKConfig(RCC_PCLK2_Div4);
// Enable ADC clock (14 MHz maximum)
// PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.666 MHz
RCC_ADCCLKConfig(RCC_PCLK2_Div6);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);

// Configure ADC
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
ADC_InitStructure.ADC_ScanConvMode = DISABLE;
ADC_InitStructure.ADC_ContinuousConvMode = DISABLE;
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
ADC_InitStructure.ADC_NbrOfChannel = 1;
ADC_Init(adc, &ADC_InitStructure);

// Enable ADC
Expand All @@ -98,31 +109,64 @@ void analogin_init(analogin_t *obj, PinName pin) {
static inline uint16_t adc_read(analogin_t *obj) {
// Get ADC registers structure address
ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc);
int channel = 0;

// Configure ADC channel
switch (obj->pin) {
case PA_0:
ADC_RegularChannelConfig(adc, ADC_Channel_0, 1, ADC_SampleTime_7Cycles5);
channel = 0;
break;
case PA_1:
ADC_RegularChannelConfig(adc, ADC_Channel_1, 1, ADC_SampleTime_7Cycles5);
channel = 1;
break;
case PA_2:
channel = 2;
break;
case PA_3:
channel = 3;
break;
case PA_4:
ADC_RegularChannelConfig(adc, ADC_Channel_4, 1, ADC_SampleTime_7Cycles5);
channel = 4;
break;
case PA_5:
channel = 5;
break;
case PA_6:
channel = 6;
break;
case PA_7:
channel = 7;
break;
case PB_0:
ADC_RegularChannelConfig(adc, ADC_Channel_8, 1, ADC_SampleTime_7Cycles5);
channel = 8;
break;
case PB_1:
channel = 9;
break;
case PC_0:
channel = 10;
break;
case PC_1:
ADC_RegularChannelConfig(adc, ADC_Channel_11, 1, ADC_SampleTime_7Cycles5);
channel = 11;
break;
case PC_0:
ADC_RegularChannelConfig(adc, ADC_Channel_10, 1, ADC_SampleTime_7Cycles5);
case PC_2:
channel = 12;
break;
case PC_3:
channel = 13;
break;
case PC_4:
channel = 14;
break;
case PC_5:
channel = 15;
break;
default:
return 0;
}

ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_7Cycles5);

ADC_SoftwareStartConvCmd(adc, ENABLE); // Start conversion

while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion
Expand Down
18 changes: 11 additions & 7 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c
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Expand Up @@ -42,12 +42,16 @@
#define LONG_TIMEOUT ((int)0x8000)

static const PinMap PinMap_I2C_SDA[] = {
{PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1
{PB_7, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)},
{PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 2)}, // GPIO_Remap_I2C1
{PB_11, I2C_2, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)},
{NC, NC, 0}
};

static const PinMap PinMap_I2C_SCL[] = {
{PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1
{PB_6, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)},
{PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 2)}, // GPIO_Remap_I2C1
{PB_10, I2C_2, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)},
{NC, NC, 0}
};

Expand Down Expand Up @@ -91,12 +95,12 @@ void i2c_frequency(i2c_t *obj, int hz) {
I2C_DeInit(i2c);

// I2C configuration
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
I2C_InitStructure.I2C_OwnAddress1 = 0;
I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
I2C_InitStructure.I2C_Mode = I2C_Mode_I2C;
I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2;
I2C_InitStructure.I2C_OwnAddress1 = 0;
I2C_InitStructure.I2C_Ack = I2C_Ack_Enable;
I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_InitStructure.I2C_ClockSpeed = hz;
I2C_InitStructure.I2C_ClockSpeed = hz;
I2C_Init(i2c, &I2C_InitStructure);

I2C_Cmd(i2c, ENABLE);
Expand Down
3 changes: 1 addition & 2 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c
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Expand Up @@ -25,8 +25,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/

extern void SystemCoreClockUpdate(void);
#include "cmsis.h"

// This function is called after RAM initialization and before main.
void mbed_sdk_init() {
Expand Down
24 changes: 13 additions & 11 deletions libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c
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Expand Up @@ -32,16 +32,18 @@
#include "error.h"

// Alternate-function mapping
static const uint32_t AF_mapping[] = {
0, // 0 = No AF
GPIO_Remap_SPI1, // 1
GPIO_Remap_I2C1, // 2
GPIO_Remap_USART1, // 3
GPIO_Remap_USART2, // 4
GPIO_FullRemap_TIM2, // 5
GPIO_FullRemap_TIM3, // 6
GPIO_PartialRemap_TIM3, // 7
GPIO_Remap_I2C1 // 8
#define AF_NUM (10)
static const uint32_t AF_mapping[AF_NUM] = {
0, // 0 = No AF
GPIO_Remap_SPI1, // 1
GPIO_Remap_I2C1, // 2
GPIO_Remap_USART1, // 3
GPIO_Remap_USART2, // 4
GPIO_PartialRemap_USART3, // 5
GPIO_PartialRemap_TIM1, // 6
GPIO_PartialRemap_TIM3, // 7
GPIO_FullRemap_TIM2, // 8
GPIO_FullRemap_TIM3 // 9
};

// Enable GPIO clock and return GPIO base address
Expand Down Expand Up @@ -93,7 +95,7 @@ void pin_function(PinName pin, int data) {

// Configure Alternate Function
// Warning: Must be done before the GPIO is initialized
if (afnum > 0) {
if ((afnum > 0) && (afnum < AF_NUM)) {
GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE);
}

Expand Down
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