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Merged
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Nov 16, 2016
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Dev stm32l0 cube v1.7.0 #3251

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ab0a8ad
STM32L0: Cube update V1.5.0 to v1.7.0
LMESTM Nov 9, 2016
fa9d147
Update Serial following L0 HAL update
LMESTM Nov 10, 2016
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8,013 changes: 5,530 additions & 2,483 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l053xx.h
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30 changes: 14 additions & 16 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l0xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.4.0
* @date 01-October-2015
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
Expand All @@ -12,8 +12,8 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
Expand Down Expand Up @@ -89,7 +89,7 @@
/* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */
/* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
/* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
/* #define STM32L061xx */ /*!< */
/* #define STM32L062xx */ /*!< STM32L062K8 */
/* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */
Expand All @@ -114,16 +114,16 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V1.2.0RC1
* @brief CMSIS Device version number V1.7.0
*/
#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32L0xx_CMSIS_VERSION_RC))

/**
* @}
Expand Down Expand Up @@ -216,8 +216,6 @@ typedef enum

#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))

/**
* @}
*/
Expand Down
34 changes: 17 additions & 17 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/stm32l0xx_hal_conf.h
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Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file stm32l0xx_hal_conf.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32l0xx_hal_conf.h.
Expand Down Expand Up @@ -90,7 +90,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

#if !defined (HSE_STARTUP_TIMEOUT)
Expand All @@ -102,22 +102,22 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */

/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
#define HSI48_VALUE ((uint32_t)48000000U) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
Expand All @@ -126,7 +126,7 @@
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)37000) /*!< LSI Typical Value in Hz*/
#define LSI_VALUE ((uint32_t)37000U) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
Expand All @@ -135,12 +135,12 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */


#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */


Expand All @@ -151,12 +151,12 @@
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define PREREAD_ENABLE 0
#define BUFFER_CACHE_DISABLE 0
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (((uint32_t)1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define PREREAD_ENABLE 0U
#define BUFFER_CACHE_DISABLE 0U

/* ########################## Assert Selection ############################## */
/**
Expand Down Expand Up @@ -296,11 +296,11 @@
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */

#ifdef __cplusplus
Expand Down
61 changes: 31 additions & 30 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.c
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Expand Up @@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32l0xx.c
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
Expand Down Expand Up @@ -40,7 +40,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -83,15 +83,15 @@
#include "hal_tick.h"

#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */

#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */

#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */


Expand All @@ -115,8 +115,8 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
This value must be a multiple of 0x100. */
/******************************************************************************/
/**
* @}
Expand Down Expand Up @@ -146,8 +146,9 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};

/**
* @}
Expand Down Expand Up @@ -179,25 +180,25 @@ uint8_t SetSysClock_PLL_HSI(void);
void SystemInit (void)
{
/*!< Set MSION bit */
RCC->CR |= (uint32_t)0x00000100;
RCC->CR |= (uint32_t)0x00000100U;

/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
RCC->CFGR &= (uint32_t) 0x88FF400C;
RCC->CFGR &= (uint32_t) 0x88FF400CU;

/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFF6;
RCC->CR &= (uint32_t)0xFEF6FFF6U;

/*!< Reset HSI48ON bit */
RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;

/*!< Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
RCC->CR &= (uint32_t)0xFFFBFFFFU;

/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
RCC->CFGR &= (uint32_t)0xFF02FFFF;
RCC->CFGR &= (uint32_t)0xFF02FFFFU;

/*!< Disable all interrupts */
RCC->CIER = 0x00000000;
RCC->CIER = 0x00000000U;

/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
Expand Down Expand Up @@ -259,33 +260,33 @@ void SystemInit (void)
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;

/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;

switch (tmp)
{
case 0x00: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
case 0x00U: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
case 0x04: /* HSI used as system clock */
case 0x04U: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock */
case 0x08U: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock */
case 0x0CU: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
pllmul = PLLMulTable[(pllmul >> 18)];
plldiv = (plldiv >> 22) + 1;
pllmul = PLLMulTable[(pllmul >> 18U)];
plldiv = (plldiv >> 22U) + 1U;

pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;

if (pllsource == 0x00)
if (pllsource == 0x00U)
{
/* HSI oscillator clock selected as PLL clock entry */
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
Expand All @@ -297,13 +298,13 @@ void SystemCoreClockUpdate (void)
}
break;
default: /* MSI used as system clock */
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
SystemCoreClock = (32768 * (1 << (msirange + 1)));
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
Expand Down
11 changes: 8 additions & 3 deletions targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device/system_stm32l0xx.h
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Expand Up @@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
Expand Down Expand Up @@ -74,6 +74,11 @@
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/*
*/
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */

/**
* @}
Expand Down
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