ARMmbed · theotherjimmy · Aug 29, 2017 · Dec 13, 2016 · Dec 16, 2016 · Dec 15, 2016
diff --git a/.travis.yml b/.travis.yml
@@ -28,10 +28,10 @@ script:
   - python tools/project.py -S
   - python tools/build_travis.py
 before_install:
-  - sudo add-apt-repository -y ppa:terry.guo/gcc-arm-embedded
+  - sudo add-apt-repository -y ppa:team-gcc-arm-embedded/ppa
   - sudo add-apt-repository -y ppa:libreoffice/libreoffice-4-2
   - sudo apt-get update -qq
-  - sudo apt-get install -qq gcc-arm-none-eabi doxygen --force-yes
+  - sudo apt-get install -qq gcc-arm-embedded doxygen --force-yes
   # Print versions we use
   - arm-none-eabi-gcc --version
   - python --version

diff --git a/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S b/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S
@@ -0,0 +1,94 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    .text
+    .global __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+__v7_all_cache:
+        .arm
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    .END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S b/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S
@@ -0,0 +1,97 @@
+/* Copyright (c) 2009 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ *      Functions
+ *---------------------------------------------------------------------------*/
+    SECTION `.text`:CODE:NOROOT(2)
+    arm 
+    PUBLIC __v7_all_cache
+/*
+ * __STATIC_ASM void __v7_all_cache(uint32_t op) {
+ */
+
+__v7_all_cache:
+
+
+        PUSH    {R4-R11}
+
+        MRC     p15, 1, R6, c0, c0, 1      /* Read CLIDR */
+        ANDS    R3, R6, #0x07000000        /* Extract coherency level */
+        MOV     R3, R3, LSR #23            /* Total cache levels << 1 */
+        BEQ     Finished                   /* If 0, no need to clean */
+
+        MOV     R10, #0                    /* R10 holds current cache level << 1 */
+Loop1:  ADD     R2, R10, R10, LSR #1       /* R2 holds cache "Set" position */
+        MOV     R1, R6, LSR R2             /* Bottom 3 bits are the Cache-type for this level */
+        AND     R1, R1, #7                 /* Isolate those lower 3 bits */
+        CMP     R1, #2
+        BLT     Skip                       /* No cache or only instruction cache at this level */
+
+        MCR     p15, 2, R10, c0, c0, 0     /* Write the Cache Size selection register */
+        ISB                                /* ISB to sync the change to the CacheSizeID reg */
+        MRC     p15, 1, R1, c0, c0, 0      /* Reads current Cache Size ID register */
+        AND     R2, R1, #7                 /* Extract the line length field */
+        ADD     R2, R2, #4                 /* Add 4 for the line length offset (log2 16 bytes) */
+        LDR     R4, =0x3FF
+        ANDS    R4, R4, R1, LSR #3         /* R4 is the max number on the way size (right aligned) */
+        CLZ     R5, R4                     /* R5 is the bit position of the way size increment */
+        LDR     R7, =0x7FFF
+        ANDS    R7, R7, R1, LSR #13        /* R7 is the max number of the index size (right aligned) */
+
+Loop2:  MOV     R9, R4                     /* R9 working copy of the max way size (right aligned) */
+
+Loop3:  ORR     R11, R10, R9, LSL R5       /* Factor in the Way number and cache number into R11 */
+        ORR     R11, R11, R7, LSL R2       /* Factor in the Set number */
+        CMP     R0, #0
+        BNE     Dccsw
+        MCR     p15, 0, R11, c7, c6, 2     /* DCISW. Invalidate by Set/Way */
+        B       cont
+Dccsw:  CMP     R0, #1
+        BNE     Dccisw
+        MCR     p15, 0, R11, c7, c10, 2    /* DCCSW. Clean by Set/Way */
+        B       cont
+Dccisw: MCR     p15, 0, R11, c7, c14, 2    /* DCCISW, Clean and Invalidate by Set/Way */
+cont:   SUBS    R9, R9, #1                 /* Decrement the Way number */
+        BGE     Loop3
+        SUBS    R7, R7, #1                 /* Decrement the Set number */
+        BGE     Loop2
+Skip:   ADD     R10, R10, #2               /* increment the cache number */
+        CMP     R3, R10
+        BGT     Loop1
+
+Finished:
+        DSB
+        POP    {R4-R11}
+        BX     lr
+
+
+    END
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
+
diff --git a/doxyfile_options b/doxyfile_options
@@ -2056,7 +2056,32 @@ INCLUDE_FILE_PATTERNS  =
 # recursively expanded use the := operator instead of the = operator.
 # This tag requires that the tag ENABLE_PREPROCESSING is set to YES.
 
-PREDEFINED             = DOXYGEN_ONLY \
+PREDEFINED             = DOXYGEN_ONLY            \
+                         DEVICE_ANALOGIN         \
+                         DEVICE_ANALOGOUT        \
+                         DEVICE_CAN              \
+                         DEVICE_ETHERNET         \
+                         DEVICE_EMAC             \
+                         DEVICE_FLASH            \
+                         DEVICE_I2C              \
+                         DEVICE_I2CSLAVE         \
+                         DEVICE_I2C_ASYNCH       \
+                         DEVICE_INTERRUPTIN      \
+                         DEVICE_LOWPOWERTIMER    \
+                         DEVICE_PORTIN           \
+                         DEVICE_PORTINOUT        \
+                         DEVICE_PORTOUT          \
+                         DEVICE_PWMOUT           \
+                         DEVICE_RTC              \
+                         DEVICE_TRNG             \
+                         DEVICE_SERIAL           \
+                         DEVICE_SERIAL_ASYNCH    \
+                         DEVICE_SERIAL_FC        \
+                         DEVICE_SLEEP            \
+                         DEVICE_SPI              \
+                         DEVICE_SPI_ASYNCH       \
+                         DEVICE_SPISLAVE         \
+                         DEVICE_STORAGE          \
                          "MBED_DEPRECATED_SINCE(d, m)=" \
                          "MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)="
 

diff --git a/doxygen_options.json b/doxygen_options.json
@@ -5,7 +5,7 @@
     "SEARCH_INCLUDES": "YES",
     "INCLUDE_PATH": "", 
     "INCLUDE_FILE_PATTERNS": "", 
-    "PREDEFINED": "DOXYGEN_ONLY \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"",
+    "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH  DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"",
     "EXPAND_AS_DEFINED": "", 
     "SKIP_FUNCTION_MACROS": "NO",
     "EXCLUDE_PATTERNS": "*/tools/* */TESTS/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */features/filesystem/* */BUILD/* */rtos/rtx*/* */cmsis/* */features/FEATURES_*"

diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md
@@ -1,5 +1,13 @@
 # Change Log
 
+## [v4.0.9](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.9) 
+
+-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.8...v4.0.9)
+
+ **Closed issues:**
+  -  IOTCLT-1899 Maximum COAP message resending buffer size limited to 255 bytes
+  -  IOTCLT-1888 Problem with blockwise transfers that are even increments of block_size
+
 ## [v4.0.8](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.0.8) 
 
 -[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.0.4...v4.0.8)

diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json
@@ -1,6 +1,6 @@
 {
   "name": "mbed-coap",
-  "version": "4.0.8",
+  "version": "4.0.9",
   "description": "COAP library",
   "keywords": [
     "coap",

diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h
@@ -225,7 +225,7 @@ struct coap_s {
     uint32_t system_time;    /* System time seconds */
     uint16_t sn_coap_block_data_size;
     uint8_t sn_coap_resending_queue_msgs;
-    uint8_t sn_coap_resending_queue_bytes;
+    uint32_t sn_coap_resending_queue_bytes;
     uint8_t sn_coap_resending_count;
     uint8_t sn_coap_resending_intervall;
     uint8_t sn_coap_duplication_buffer_size;

diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c
@@ -2027,7 +2027,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
                 original_payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len;
                 original_payload_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr;
 
-                if ((block_size * (block_number + 1)) > stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
+                if ((block_size * (block_number + 1)) >= stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
                     src_coap_blockwise_ack_msg_ptr->payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len - (block_size * block_number);
                     src_coap_blockwise_ack_msg_ptr->payload_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr + (block_size * block_number);
                 }
@@ -2080,7 +2080,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn
                 stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len = original_payload_len;
                 stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr = original_payload_ptr;
 
-                if ((block_size * (block_number + 1)) > stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
+                if ((block_size * (block_number + 1)) >= stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) {
                     sn_coap_protocol_linked_list_blockwise_msg_remove(handle, stored_blockwise_msg_temp_ptr);
                 }
 

diff --git a/...ures/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/lwipopts_conf.h b/...ures/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/lwipopts_conf.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2012-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ * 
+ * http://www.apache.org/licenses/LICENSE-2.0
+ * 
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef LWIPOPTS_CONF_H
+#define LWIPOPTS_CONF_H
+
+#define LWIP_TRANSPORT_ETHERNET       1
+#define ETH_PAD_SIZE                  2
+
+#define MEM_SIZE                      (16*1024)//(8*1024)//(16*1024)
+
+#endif