Release candidate for mbed-os-5.6.0-rc2

features/FEATURE_LWIP/TESTS/mbedmicro-net/tcp_hello_world/main.cpp

@@ -33,7 +33,7 @@ using namespace utest::v1;
 
 namespace {
     // Test connection information
-    const char *HTTP_SERVER_NAME = "developer.mbed.org";
+    const char *HTTP_SERVER_NAME = "os.mbed.com";
     const char *HTTP_SERVER_FILE_PATH = "/media/uploads/mbed_official/hello.txt";
     const int HTTP_SERVER_PORT = 80;
 #if defined(TARGET_VK_RZ_A1H)

features/FEATURE_LWIP/lwip-interface/mbed_lib.json

@@ -84,5 +84,10 @@
             "help": "Thread stack size for PPP",
             "value": 768
         }
+    },
+    "target_overrides": {
+        "REALTEK_RTL8195AM": {
+            "tcpip-thread-stacksize": 1600
+        }
     }
 }

features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp

@@ -141,7 +141,7 @@ static void CMT_URC(ATCmdParser *at)
 
 static bool set_atd(ATCmdParser *at)
 {
-    bool success = at->send("ATD*99***" CTX"#") && at->recv("CONNECT");
+    bool success = at->send("ATD*99***" CTX "#") && at->recv("CONNECT");
 
     return success;
 }
@@ -469,7 +469,7 @@ nsapi_error_t PPPCellularInterface::setup_context_and_credentials()
 #endif
     success = _at->send("AT"
                           "+FCLASS=0;" // set to connection (ATD) to data mode
-                          "+CGDCONT=" CTX",\"%s\",\"%s%s\"",
+                          "+CGDCONT=" CTX ",\"%s\",\"%s%s\"",
                           pdp_type, auth, _apn
                          )
                    && _at->recv("OK");

rtos/TARGET_CORTEX/mbed_rtx_idle.cpp

@@ -195,6 +195,14 @@ static void default_idle_hook(void)
     core_util_critical_section_exit();
 }
 
+#elif defined(FEATURE_UVISOR)
+
+static void default_idle_hook(void)
+{
+    /* uVisor can't sleep. See <https://github.com/ARMmbed/uvisor/issues/420>
+     * for details. */
+}
+
 #else
 
 static void default_idle_hook(void)

rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S

@@ -0,0 +1,298 @@
+;/*
+; * Copyright (c) 2016-2017 ARM Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; * -----------------------------------------------------------------------------
+; *
+; * Project:     CMSIS-RTOS RTX
+; * Title:       ARMv8M Baseline Exception handlers
+; *
+; * -----------------------------------------------------------------------------
+; */
+
+I_T_RUN_OFS     EQU      28                     ; osInfo.thread.run offset
+TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
+TCB_SP_OFS      EQU      56                     ; TCB.SP offset
+TCB_SF_OFS      EQU      34                     ; TCB.stack_frame offset
+TCB_TZM_OFS     EQU      64                     ; TCB.tz_memory offset
+
+
+                PRESERVE8
+                THUMB
+
+
+                AREA     |.constdata|, DATA, READONLY
+                EXPORT   irqRtxLib
+irqRtxLib       DCB      0                      ; Non weak library reference
+
+
+                AREA     |.text|, CODE, READONLY
+
+
+SVC_Handler     PROC
+                EXPORT   SVC_Handler
+                IMPORT   osRtxUserSVC
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                MRS      R0,PSP                 ; Get PSP
+                LDR      R1,[R0,#24]            ; Load saved PC from stack
+                SUBS     R1,R1,#2               ; Point to SVC instruction
+                LDRB     R1,[R1]                ; Load SVC number
+                CMP      R1,#0
+                BNE      SVC_User               ; Branch if not SVC 0
+
+                PUSH     {R0,LR}                ; Save PSP and EXC_RETURN
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R7                     ; Call service function
+                POP      {R2,R3}                ; Restore PSP and EXC_RETURN
+                STMIA    R2!,{R0-R1}            ; Store function return values
+                MOV      LR,R3                  ; Set EXC_RETURN
+
+SVC_Context
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDMIA    R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      SVC_Exit               ; Branch when threads are the same
+
+                CBZ      R1,SVC_ContextSwitch   ; Branch if running thread is deleted
+
+SVC_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+#endif
+
+SVC_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+SVC_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+SVC_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.thread.run: curr = next
+
+SVC_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,SVC_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+SVC_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      SVC_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+SVC_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+SVC_Exit
+                BX       LR                     ; Exit from handler
+
+SVC_User
+                PUSH     {R4,LR}                ; Save registers
+                LDR      R2,=osRtxUserSVC       ; Load address of SVC table
+                LDR      R3,[R2]                ; Load SVC maximum number
+                CMP      R1,R3                  ; Check SVC number range
+                BHI      SVC_Done               ; Branch if out of range
+
+                LSLS     R1,R1,#2
+                LDR      R4,[R2,R1]             ; Load address of SVC function
+
+                LDM      R0,{R0-R3}             ; Load function parameters from stack
+                BLX      R4                     ; Call service function
+                MRS      R4,PSP                 ; Get PSP
+                STR      R0,[R4]                ; Store function return value
+
+SVC_Done
+                POP      {R4,PC}                ; Return from handler
+
+                ALIGN
+                ENDP
+
+
+PendSV_Handler  PROC
+                EXPORT   PendSV_Handler
+                IMPORT   osRtxPendSV_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxPendSV_Handler    ; Call osRtxPendSV_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+SysTick_Handler PROC
+                EXPORT   SysTick_Handler
+                IMPORT   osRtxTick_Handler
+
+                PUSH     {R0,LR}                ; Save EXC_RETURN
+                BL       osRtxTick_Handler      ; Call osRtxTick_Handler
+                POP      {R0,R1}                ; Restore EXC_RETURN
+                MOV      LR,R1                  ; Set EXC_RETURN
+                B        Sys_Context
+
+                ALIGN
+                ENDP
+
+
+Sys_Context     PROC
+                EXPORT   Sys_Context
+                IMPORT   osRtxInfo
+#ifdef __DOMAIN_NS
+                IMPORT   TZ_LoadContext_S
+                IMPORT   TZ_StoreContext_S
+#endif
+
+                LDR      R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run
+                LDM      R3!,{R1,R2}            ; Load osRtxInfo.thread.run: curr & next
+                CMP      R1,R2                  ; Check if thread switch is required
+                BEQ      Sys_ContextExit        ; Branch when threads are the same
+
+Sys_ContextSave
+#ifdef __DOMAIN_NS
+                LDR      R0,[R1,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextSave1    ; Branch if there is no secure context
+                PUSH     {R1,R2,R3,R7}          ; Save registers
+                MOV      R7,LR                  ; Get EXC_RETURN
+                BL       TZ_StoreContext_S      ; Store secure context
+                MOV      LR,R7                  ; Set EXC_RETURN
+                POP      {R1,R2,R3,R7}          ; Restore registers
+                LSLS     R7,R7,#25              ; Check domain of interrupted thread
+                BMI      Sys_ContextSave1       ; Branch if secure
+                MRS      R0,PSP                 ; Get PSP
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                B        Sys_ContextSave2
+#endif
+
+Sys_ContextSave1
+                MRS      R0,PSP                 ; Get PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                STR      R0,[R1,#TCB_SP_OFS]    ; Store SP
+                STMIA    R0!,{R4-R7}            ; Save R4..R7
+                MOV      R4,R8
+                MOV      R5,R9
+                MOV      R6,R10
+                MOV      R7,R11
+                STMIA    R0!,{R4-R7}            ; Save R8..R11
+
+Sys_ContextSave2
+                MOV      R0,LR                  ; Get EXC_RETURN
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust address
+                STRB     R0,[R1]                ; Store stack frame information
+
+Sys_ContextSwitch
+                SUBS     R3,R3,#8               ; Adjust address
+                STR      R2,[R3]                ; osRtxInfo.run: curr = next
+
+Sys_ContextRestore
+#ifdef __DOMAIN_NS
+                LDR      R0,[R2,#TCB_TZM_OFS]   ; Load TrustZone memory identifier
+                CBZ      R0,Sys_ContextRestore1 ; Branch if there is no secure context
+                PUSH     {R2,R3}                ; Save registers
+                BL       TZ_LoadContext_S       ; Load secure context
+                POP      {R2,R3}                ; Restore registers
+#endif
+
+Sys_ContextRestore1
+                MOV      R1,R2
+                ADDS     R1,R1,#TCB_SF_OFS      ; Adjust offset
+                LDRB     R0,[R1]                ; Load stack frame information
+                MOVS     R1,#0xFF
+                MVNS     R1,R1                  ; R1=0xFFFFFF00
+                ORRS     R0,R1
+                MOV      LR,R0                  ; Set EXC_RETURN
+
+#ifdef __DOMAIN_NS
+                LSLS     R0,R0,#25              ; Check domain of interrupted thread
+                BPL      Sys_ContextRestore2    ; Branch if non-secure
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                MSR      PSP,R0                 ; Set PSP
+                BX       LR                     ; Exit from handler
+#else
+                LDR      R0,[R2,#TCB_SM_OFS]    ; Load stack memory base
+                MSR      PSPLIM,R0              ; Set PSPLIM
+#endif
+
+Sys_ContextRestore2
+                LDR      R0,[R2,#TCB_SP_OFS]    ; Load SP
+                ADDS     R0,R0,#16              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R8..R11
+                MOV      R8,R4
+                MOV      R9,R5
+                MOV      R10,R6
+                MOV      R11,R7
+                MSR      PSP,R0                 ; Set PSP
+                SUBS     R0,R0,#32              ; Adjust address
+                LDMIA    R0!,{R4-R7}            ; Restore R4..R7
+
+Sys_ContextExit
+                BX       LR                     ; Exit from handler
+
+                ALIGN
+                ENDP
+
+
+                END

targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct

@@ -19,7 +19,7 @@ LR_IROM1 0x1B000 0x0025000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20002FB8 0x00005048  {
    .ANY (+RW +ZI)

targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct

@@ -19,7 +19,7 @@ LR_IROM1 0x18000 0x0028000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002000 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x200020C0 0x00001F40  {
    .ANY (+RW +ZI)

targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct

@@ -19,7 +19,7 @@ LR_IROM1 0x0001B000 0x0025000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20002FB8 0x00001048  {
    .ANY (+RW +ZI)

targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/nRF52832.sct

@@ -19,7 +19,7 @@ LR_IROM1 0x1C000 0x0064000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20002EF8 UNINIT 0x000000D8  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20002FD0 0x0000D030  {
    .ANY (+RW +ZI)

targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct

@@ -5,7 +5,7 @@ LR_IROM1 0x21000 0x00DF000  {
    .ANY (+RO)
   }
   RW_IRAM0 0x20003288 UNINIT 0x000000F8  { ;no init section
-        *(noinit)
+        *(*noinit)
   }
   RW_IRAM1 0x20003380 0x0003cc80  {
    .ANY (+RW +ZI)