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Add memory barriers to STM32F7xx Ethernet #5720

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Merged
merged 1 commit into from
Dec 22, 2017
Merged

Add memory barriers to STM32F7xx Ethernet #5720

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7 changes: 7 additions & 0 deletions targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c
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Original file line number Diff line number Diff line change
Expand Up @@ -717,6 +717,8 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
/* Ensure rest of descriptor is written to RAM before the OWN bit */
__DMB();
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* Point to next descriptor */
Expand Down Expand Up @@ -746,13 +748,18 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
}

/* Ensure rest of descriptor is written to RAM before the OWN bit */
__DMB();
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
}
}

/* Ensure all descriptors are written to RAM before checking transmitter status */
__DMB();

/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
{
Expand Down