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Merged
merged 22 commits into from
May 24, 2018
Merged

Update cmsis/rtx to version 5.3 #6273

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8afbd66
[CMSIS_5]: Updated to 49ac527a
bulislaw Mar 1, 2018
4360b7b
CMSIS/RTX: Patch RTX4 to preserve osThreadDef compatibility
bulislaw Jul 4, 2017
cc2e051
CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets
bulislaw Jul 4, 2017
b882548
CMSIS/RTX: Allow overwriting mutex ops for ARMC
bulislaw Oct 18, 2017
287121f
CMSIS/RTX: Pre-processor defines used for assembly
Feb 7, 2018
07aad3c
CMSIS/RTX: Adapt Mbed OS to CMSIS/RTX device support scheme
bulislaw Mar 1, 2018
3f1ea4b
CMSIS/RTX: Update idle handler and SysTick ops
bulislaw Mar 1, 2018
cb2b91c
CMSIS/RTX: uVisor: Import v0.30.0
Patater Aug 14, 2017
73a9579
RTX5: uVisor: Switch threads very carefully
Patater May 25, 2017
c250369
RTX5: uVisor: Use OsEventObserver
Patater Jan 19, 2017
86b91be
RTX5: uVisor: Extend thread control block with context
Patater Jan 25, 2017
32d04a0
RTX5: uVisor: Add OsEventObserver
Patater Jan 19, 2017
2f7a841
RTX5: uVisor: Defer to uVisor for SVCall priority
Patater Jan 30, 2017
a1fb51c
RTX5: uVisor: Remove static from svcRtxKernelUnlock/Lock to support u…
bulislaw May 11, 2018
1752803
CMSIS/RTX: Fix using FALSE/TRUE with preprocesor
bulislaw Apr 30, 2018
6a6e3ac
CMSIS/RTX: Reintroduce arm_math.h
bulislaw May 11, 2018
31eee7d
Fix cmsis_importer.json so it works with the newest CMSIS
bulislaw Mar 1, 2018
00a3218
Rename __DOMAIN_NS to DOMAIN_NS to match CMSIS
bulislaw Apr 26, 2018
b4d5f0e
CMSIS: Move non-config includes behind PTIM ifdef
bulislaw Mar 1, 2018
38df930
Update wsf_types.h to support updated CMSIS
bulislaw Apr 30, 2018
42b4882
Fix platform failing to build after rebase
bulislaw May 11, 2018
076cd42
Update uvisor-tests.txt
orenc17 May 22, 2018
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13 changes: 2 additions & 11 deletions cmsis/RTE_Components.h
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Expand Up @@ -18,16 +18,7 @@

#define CMSIS_device_header <cmsis.h>

#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE
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@bulislaw - Looks like something went wrong with rebase/merge. These defines were recently added to RTE_Components.h and should not be deleted.

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Nope, I've just moved it to the right place - aka config file. Let me know if there's specific reason it shouldn't be in the config file.

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These defines are used to build secure binary for v8 devices and we do not have RTOS support in secure mode. Conf file is not accessible if you add "RTOS" folder in .mbedignore

#define MBED_CONF_TZ_PROCESS_STACK_SIZE 512
#endif
#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS
#define MBED_CONF_TZ_PROCESS_STACK_SLOTS 8
#endif

#define TZ_PROCESS_STACK_SLOTS MBED_CONF_TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SIZE MBED_CONF_TZ_PROCESS_STACK_SIZE
#include "mbed_rtx_conf.h"
#include "mbed_cmsis_conf.h"

#endif


8 changes: 4 additions & 4 deletions cmsis/TARGET_CORTEX_A/cmsis_armcc.h
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@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 07. Sep 2017
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand All @@ -26,7 +26,7 @@
#define __CMSIS_ARMCC_H

#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif

/* CMSIS compiler control architecture macros */
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8 changes: 4 additions & 4 deletions cmsis/TARGET_CORTEX_A/cmsis_armclang.h
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@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 07. Sep 2017
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand All @@ -28,7 +28,7 @@
#pragma clang system_header /* treat file as system include file */

#ifndef __ARM_COMPAT_H
#include <arm_compat.h> /* Compatibility header for ARM Compiler 5 intrinsics */
#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
#endif

/* CMSIS compiler specific defines */
Expand Down
12 changes: 6 additions & 6 deletions cmsis/TARGET_CORTEX_A/cmsis_compiler.h
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@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 01. December 2017
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand All @@ -28,14 +28,14 @@
#include <stdint.h>

/*
* ARM Compiler 4/5
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"


/*
* ARM Compiler 6 (armclang)
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
Expand All @@ -56,7 +56,7 @@


/*
* TI ARM Compiler
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
Expand Down
51 changes: 47 additions & 4 deletions cmsis/TARGET_CORTEX_A/cmsis_cp15.h
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Expand Up @@ -223,7 +223,7 @@ __STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
return result;
}

/** \brief Get VBAR
/** \brief Get VBAR

This function returns the value of the Vector Base Address Register.

Expand All @@ -244,7 +244,31 @@ __STATIC_FORCEINLINE uint32_t __get_VBAR(void)
*/
__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
{
__set_CP(15, 0, vbar, 12, 0, 1);
__set_CP(15, 0, vbar, 12, 0, 0);
}

/** \brief Get MVBAR

This function returns the value of the Monitor Vector Base Address Register.

\return Monitor Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 1);
return result;
}

/** \brief Set MVBAR

This function assigns the given value to the Monitor Vector Base Address Register.

\param [in] mvbar Monitor Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
{
__set_CP(15, 0, mvbar, 12, 0, 1);
}

#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
Expand Down Expand Up @@ -413,13 +437,32 @@ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
__set_CP(15, 0, value, 7, 14, 1);
}

/** \brief Set CSSELR
*/
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
{
// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
__set_CP(15, 2, value, 0, 0, 0);
}

/** \brief Get CSSELR
\return CSSELR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
__get_CP(15, 2, result, 0, 0, 0);
return result;
}

/** \brief Set CCSIDR
\deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
*/
CMSIS_DEPRECATED
__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
{
// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
__set_CP(15, 2, value, 0, 0, 0);
__set_CSSELR(value);
}

/** \brief Get CCSIDR
Expand Down
2 changes: 1 addition & 1 deletion cmsis/TARGET_CORTEX_A/cmsis_gcc.h
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Expand Up @@ -642,7 +642,7 @@ __STATIC_INLINE void __FPU_Enable(void)
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"

#if __ARM_NEON == 1
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
Expand Down
8 changes: 4 additions & 4 deletions cmsis/TARGET_CORTEX_A/cmsis_iccarm.h
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@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR compiler) header file
* @version V5.0.4
* @date 01. December 2017
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.5
* @date 10. January 2018
******************************************************************************/

//------------------------------------------------------------------------------
//
// Copyright (c) 2017 IAR Systems
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
Expand Down
8 changes: 4 additions & 4 deletions cmsis/TARGET_CORTEX_A/core_ca.h
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Expand Up @@ -950,8 +950,8 @@ __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
*/
__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
{
register volatile uint32_t Dummy;
register volatile uint32_t ccsidr;
uint32_t Dummy;
uint32_t ccsidr;
uint32_t num_sets;
uint32_t num_ways;
uint32_t shift_way;
Expand All @@ -960,7 +960,7 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma

Dummy = level << 1U;
/* set csselr, select ccsidr register */
__set_CCSIDR(Dummy);
__set_CSSELR(Dummy);
/* get current ccsidr register */
ccsidr = __get_CCSIDR();
num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
Expand Down Expand Up @@ -992,7 +992,7 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
*/
__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
register volatile uint32_t clidr;
uint32_t clidr;
uint32_t cache_type;
clidr = __get_CLIDR();
for(uint32_t i = 0U; i<7U; i++)
Expand Down
6 changes: 6 additions & 0 deletions cmsis/TARGET_CORTEX_A/irq_ctrl.h
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Expand Up @@ -22,6 +22,12 @@
* limitations under the License.
*/

#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif

#ifndef IRQ_CTRL_H_
#define IRQ_CTRL_H_

Expand Down
15 changes: 8 additions & 7 deletions cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c
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Expand Up @@ -24,7 +24,8 @@

#include <stddef.h>

#include <cmsis.h>
#include "RTE_Components.h"
#include CMSIS_device_header

#include "irq_ctrl.h"

Expand Down Expand Up @@ -125,13 +126,11 @@ __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {

/// Configure interrupt request mode.
__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
int32_t status;
uint32_t val;
uint8_t cfg;
uint8_t secure;
uint8_t cpu;

status = 0;
int32_t status = 0;

if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
// Check triggering mode
Expand All @@ -142,6 +141,7 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
} else if (val == IRQ_MODE_TRIG_EDGE) {
cfg = 0x02U;
} else {
cfg = 0x00U;
status = -1;
}

Expand All @@ -156,15 +156,16 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
val = mode & IRQ_MODE_DOMAIN_Msk;

if (val == IRQ_MODE_DOMAIN_NONSECURE) {
secure = 0;
secure = 0U;
} else {
// Check security extensions support
val = GIC_DistributorInfo() & (1UL << 10U);

if (val != 0U) {
// Security extensions are supported
secure = 1;
secure = 1U;
} else {
secure = 0U;
status = -1;
}
}
Expand All @@ -173,7 +174,7 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
val = mode & IRQ_MODE_CPU_Msk;

if (val == IRQ_MODE_CPU_ALL) {
cpu = 0xFF;
cpu = 0xFFU;
} else {
cpu = val >> IRQ_MODE_CPU_Pos;
}
Expand Down
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