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Cellular: HSI set to be source clock for WISE_1570 #7489
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Cellular: HSI set to be source clock for WISE_1570 #7489
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@JanneKiiskila @mirelachirica We're having some issues with the testing CI atm. Will start once they're resolved. |
Can you check PR #7498 ? Thanks. |
/morph build |
@bcostm Who are you referring to when you say "you"? |
@bcostm @jeromecoutant @JanneKiiskila @mirelachirica @bcostm @jeromecoutant Do y'all have any strong arguments as to why this needs to wait on #7498? |
This can be done in 2 steps. |
Build : SUCCESSBuild number : 2586 Triggering tests/morph test |
Exporter Build : FAILUREBuild number : 2229 |
Export failure due to multiply defined symbols, but symbol does not appear related tio PR. |
Exporter Build : SUCCESSBuild number : 2232 |
Test : SUCCESSBuild number : 2340 |
Hello, I'm having an issue with this fix. The board MTB_ADV_WISE_1570 fails in SetSysClock_PLL_HSI in function HAL_RCC_OscConfig. More precisely this happens when waiting the PLL to stabilize (stm32l4xx_hal_rcc.c:813). As a workaround increasing PLL_TIMEOUT_VALUE from 2ms to 5ms solves the issue. Then it works 10/10 tries. With 4ms value it works 1/20 times. If changing the PLL timeout value is a valid fix, maybe the timeout value could be as parameter to HAL_RCC_OscConfig? |
@juhoeskeli Would you mind opening an issue and referencing this PR if you haven't already? Comments left in PRs after they're merged tend not to get the best attention. |
@cmonr Sounds fair. |
@cmonr I noticed that the issue was due to bootloader using different clock and then switching to HSI in application. By using the same clock in bootloader there is no issue. I consider this working as intended. |
…ce_clock Cellular: HSI set to be source clock for WISE_1570
Description
LSE as LPUART source clock is causing WISE_1570 to have stability issues(framing errors) for AT commands communication over LPUART. Changing clock to HSI is fixing the problem.
Internal defect: IOTCELL-988
Pull request type