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Timer: fix to init in non-critical context #8502
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…dware timer in non-critical context.
Is this the only issue you are having with this target - the rest of drivers are fine? Basically, this is one extra step (that is done in the reset method but that one is within critical section) added. |
During tests on our platform I haven't found other driver issues. I guess only Timer is using critical section. |
This change might have impact on ARMv8 devices as well. CC @ARMmbed/team-nuvoton @gaborkertesz |
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@lrusinowicz if this is a requirement for your target I would recommend calling the ticker initialization as part of the boot sequence rather than when a Timer
is created. That will ensure that all users of the ticker work correctly, rather than just Timer
. I recommend placing the ticker initialization in the hook mbed_sdk_init
.
This is what should be considered. I assumed that this is much bigger problem we might facing. Please review |
Many HAL device calls are expected to be interrupt safe - useable from interrupts, and with interrupts disabled. Hence tweaks like this being needed: #8048 I think you may ultimately need to have polling comms mechanism that can be invoked for cases where you're in a critical section and need to talk to the other core, but maybe if it's init only that can be avoided. For this case, if the problem only occurs on first call, this sort of fix seems reasonable - make sure a call happens early so all subsequent ones are safe, but not sure this is the correct place for it. It could result in interleaving calls to the Simplest thing to do would just be to do the necessary init yourself in platform startup code, before entering Calling |
@lrusinowicz I believe this was resolved differently and this one is not needed anymore (as it is) ? |
@0xc0170 Yes, it's not needed for Sequana. Should I close it? |
…dware timer in non-critical context.
This benefits target platforms having multiple MCUs/cores but shared other hardware resources - in this case timers.
Probably the first example of such platform is Cypress PSoC 6 MCU on Future Electronics Sequana board (upcoming new target). Implementation of hardware resource manager on this platform prevents initialization of hardware resources on M4 core in a critical/interrupt context, because it involves communication with M0 core to synchronize on resource usage.
Notice, that this is critical fix for this platform
@MarceloSalazar
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