STM32F429/STM32F439 alignment

features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/LICENSE

@@ -0,0 +1,49 @@
+Permissive Binary License
+
+Version 1.0, September 2015
+
+Redistribution.  Redistribution and use in binary form, without
+modification, are permitted provided that the following conditions are
+met:
+
+1) Redistributions must reproduce the above copyright notice and the
+   following disclaimer in the documentation and/or other materials
+   provided with the distribution.
+
+2) Unless to the extent explicitly permitted by law, no reverse
+   engineering, decompilation, or disassembly of this software is
+   permitted.
+
+3) Redistribution as part of a software development kit must include the
+   accompanying file named "DEPENDENCIES" and any dependencies listed in
+   that file.
+
+4) Neither the name of the copyright holder nor the names of its
+   contributors may be used to endorse or promote products derived from
+   this software without specific prior written permission. 
+
+Limited patent license. The copyright holders (and contributors) grant a
+worldwide, non-exclusive, no-charge, royalty-free patent license to
+make, have made, use, offer to sell, sell, import, and otherwise
+transfer this software, where such license applies only to those patent
+claims licensable by the copyright holders (and contributors) that are
+necessarily infringed by this software. This patent license shall not
+apply to any combinations that include this software.  No hardware is
+licensed hereunder.
+
+If you institute patent litigation against any entity (including a
+cross-claim or counterclaim in a lawsuit) alleging that the software
+itself infringes your patent(s), then your rights granted under this
+license shall terminate as of the date such litigation is filed.
+
+DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
+NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

features/FEATURE_BOOTLOADER/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/mbed_lib.json

@@ -0,0 +1,10 @@
+{
+    "name": "bootloader_NUCLEO_F439ZI",
+    "target_overrides": {
+        "*": {
+            "target.app_offset": "0x10400",
+            "target.header_offset": "0x10000",
+            "target.bootloader_img": "mbed-bootloader-nucleo_f439zi-block_device-sotp-v3_4_0.bin"
+        }
+    }
+}

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c

@@ -30,7 +30,7 @@
 **/
 
 #include "stm32f4xx.h"
-
+#include "nvic_addr.h"
 #include "mbed_error.h"
 
 // clock source is selected with CLOCK_SOURCE in json config
@@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void);
   */
 void SystemInit(void)
 {
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
     /* Reset the RCC clock configuration to the default reset state ------------*/
     /* Set HSION bit */
     RCC->CR |= (uint32_t)0x00000001;
@@ -79,6 +83,13 @@ void SystemInit(void)
     SystemInit_ExtMemCtl();
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
 }
 
 /**

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c

@@ -30,7 +30,7 @@
 **/
 
 #include "stm32f4xx.h"
-
+#include "nvic_addr.h"
 #include "mbed_error.h"
 
 // clock source is selected with CLOCK_SOURCE in json config
@@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void);
   */
 void SystemInit(void)
 {
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
+#endif
     /* Reset the RCC clock configuration to the default reset state ------------*/
     /* Set HSION bit */
     RCC->CR |= (uint32_t)0x00000001;
@@ -79,6 +83,13 @@ void SystemInit(void)
     SystemInit_ExtMemCtl();
 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
 }
 
 /**

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S

@@ -168,15 +168,9 @@ __Vectors_Size  EQU  __Vectors_End - __Vectors
 ; Reset handler
 Reset_Handler    PROC
                  EXPORT  Reset_Handler             [WEAK]
-        IMPORT  SystemInitPre
-        IMPORT  HAL_InitPre
         IMPORT  SystemInit
         IMPORT  __main
 
-                 LDR     R0, =SystemInitPre
-                 BLX     R0
-                 LDR     R0, =HAL_InitPre
-                 BLX     R0
                  LDR     R0, =SystemInit
                  BLX     R0
                  LDR     R0, =__main

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/stm32f429xx.sct

@@ -45,7 +45,7 @@
 #define MBED_RAM0_START             (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
 #define MBED_RAM0_SIZE              (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
 
-; 2 MB FLASH (0x200000) + 192 KB SRAM (0x30000)
+; 2 MB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
 LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
 
   ER_IROM1 MBED_APP_START MBED_APP_SIZE  {  ; load address = execution address
@@ -61,6 +61,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE  {    ; load region size_region
   RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE)  {  ; RW data
    .ANY (+RW +ZI)
   }
-
+
+  RW_IRAM2 (0x10000000) (0x10000)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
 }
 

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/STM32F429xI.ld

@@ -1,11 +1,3 @@
-M_VECTOR_RAM_SIZE = 0x400;
-
-/* With the RTOS in use, this does not affect the main stack size. The size of
- * the stack where main runs is determined via the RTOS. */
-STACK_SIZE = 0x400;
-
-HEAP_SIZE = 0x6000;
-
 #if !defined(MBED_APP_START)
   #define MBED_APP_START 0x08000000
 #endif
@@ -16,13 +8,13 @@ HEAP_SIZE = 0x6000;
 
 M_CRASH_DATA_RAM_SIZE = 0x100;
 
-/* Specify the memory areas */
+/* Linker script to configure memory regions. */
+/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/
 MEMORY
-{
-    VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x400
-    FLASH (rx)   : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
-    CCM (rwx)    : ORIGIN = 0x10000000, LENGTH = 64K
-    RAM (rwx)    : ORIGIN = 0x20000000, LENGTH = 192k
+{ 
+  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+  CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+  RAM (rwx) : ORIGIN = 0x200001B0, LENGTH = 192k - (0x1AC+0x4)
 }
 
 /* Linker script to place sections and symbol values. Should be used together
@@ -56,18 +48,10 @@ ENTRY(Reset_Handler)
 
 SECTIONS
 {
-    .isr_vector :
-    {
-        __vector_table = .;
-        KEEP(*(.isr_vector))
-         . = ALIGN(8);
-    } > VECTORS
-
     .text :
     {
-
+        KEEP(*(.isr_vector))
         *(.text*)
-
         KEEP(*(.init))
         KEEP(*(.fini))
 
@@ -96,7 +80,6 @@ SECTIONS
     } > FLASH
 
     __exidx_start = .;
-
     .ARM.exidx :
     {
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
@@ -105,17 +88,6 @@ SECTIONS
 
     __etext = .;
     _sidata = .;
-
-    .interrupts_ram :
-    {
-        . = ALIGN(8);
-        __VECTOR_RAM__ = .;
-        __interrupts_ram_start__ = .; /* Create a global symbol at data start */
-        *(.m_interrupts_ram)     /* This is a user defined section */
-        . += M_VECTOR_RAM_SIZE;
-        . = ALIGN(8);
-        __interrupts_ram_end__ = .; /* Define a global symbol at data end */
-    } > RAM
 
     .crash_data_ram :
     {
@@ -127,12 +99,10 @@ SECTIONS
         . += M_CRASH_DATA_RAM_SIZE;
         . = ALIGN(8);
         __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
-    } > RAM    
+    } > RAM        
 
-    .data :
+    .data : AT (__etext)
     {
-        PROVIDE( __etext = LOADADDR(.data) );
-
         __data_start__ = .;
         _sdata = .;
         *(vtable)
@@ -165,23 +135,9 @@ SECTIONS
         __data_end__ = .;
         _edata = .;
 
-    } > RAM AT > FLASH
-
-
-    /* Uninitialized data section
-     * This region is not initialized by the C/C++ library and can be used to
-     * store state across soft reboots. */
-    .uninitialized (NOLOAD):
-    {
-        . = ALIGN(32);
-        __uninitialized_start = .;
-        *(.uninitialized)
-        KEEP(*(.keep.uninitialized))
-        . = ALIGN(32);
-        __uninitialized_end = .;
     } > RAM
 
-    .bss (NOLOAD):
+    .bss :
     {
         . = ALIGN(8);
         __bss_start__ = .;
@@ -193,18 +149,29 @@ SECTIONS
         _ebss = .;
     } > RAM
 
-    .heap (NOLOAD):
+    .heap (COPY):
     {
         __end__ = .;
         end = __end__;
-        . += HEAP_SIZE;
+        *(.heap*)
         __HeapLimit = .;
     } > RAM
 
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __stack = __StackTop;
-    __StackLimit = __StackTop - STACK_SIZE;
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
 
-    ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
 
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
 }

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S

@@ -74,10 +74,10 @@ defined in linker script */
     .section  .text.Reset_Handler
   .weak  Reset_Handler
   .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   sp, =__stack       /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
+Reset_Handler: 
+  ldr   sp, =_estack       /* set stack pointer */
+ 
+/* Copy the data segment initializers from flash to SRAM */  
   movs  r1, #0
   b  LoopCopyDataInit
 
@@ -106,8 +106,6 @@ LoopFillZerobss:
   bcc  FillZerobss
 
 /* Call the clock system intitialization function.*/
-  bl SystemInitPre
-  bl HAL_InitPre
   bl  SystemInit   
 /* Call static constructors */
   //bl __libc_init_array
@@ -142,10 +140,10 @@ Infinite_Loop:
 *******************************************************************************/
    .section  .isr_vector,"a",%progbits
   .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-   
-g_pfnVectors:
-  .word  __stack
+  .size  g_pfnVectors, .-g_pfnVectors 
+
+  g_pfnVectors:
+  .word  _estack
   .word  Reset_Handler
 
   .word  NMI_Handler
@@ -212,7 +210,7 @@ g_pfnVectors:
   .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
   .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
   .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
-  .word     FMC_IRQHandler                    /* FMC                         */                   
+  .word     FMC_IRQHandler                    /* FMC                          */                   
   .word     SDIO_IRQHandler                   /* SDIO                         */                   
   .word     TIM5_IRQHandler                   /* TIM5                         */                   
   .word     SPI3_IRQHandler                   /* SPI3                         */                   
@@ -252,8 +250,8 @@ g_pfnVectors:
   .word     SPI5_IRQHandler                   /* SPI5 						  */
   .word     SPI6_IRQHandler                   /* SPI6						  */
   .word     SAI1_IRQHandler                   /* SAI1						  */
-  .word     LTDC_IRQHandler                   /* LTDC_IRQHandler			  */
-  .word     LTDC_ER_IRQHandler                /* LTDC_ER_IRQHandler			  */
+  .word     LTDC_IRQHandler                   /* LTDC           		      */
+  .word     LTDC_ER_IRQHandler                /* LTDC error          	      */
   .word     DMA2D_IRQHandler                  /* DMA2D                        */
 
 /*******************************************************************************