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stm32l475: lwip symbols in sram1 #9793

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823db2d
stm32l475: lwip symbols in sram1
Feb 21, 2019
78837ef
Adjust HEAP dynamically with IAR 8.x
Mar 4, 2019
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1 change: 1 addition & 0 deletions ...ets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct
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Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
}
RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size { ; RW data 96k L4-SRAM1
.ANY (+RW, +Last)
lwip* (+ZI)
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@deepikabhavnani deepikabhavnani Mar 6, 2019 •
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ARM compiler supports expansion of RW and ZI in multiple banks, please try below solution

RW_IRAM1 MBED_RAM0_START MBED_RAM0_SIZE-Stack_Size  { ; RW data 96k L4-SRAM1
   .ANY (+RW +ZI)
  }
 ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
  RW_IRAM2 (0x10000000+0x188) (0x08000-0x188)  {  ; ZI data 32k L4-ECC-SRAM2
   .ANY (+RW +ZI)
  }

}
; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM
RW_IRAM2 (0x10000000+0x188) (0x08000-0x188) { ; ZI data 32k L4-ECC-SRAM2
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10 changes: 10 additions & 0 deletions targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld
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Expand Up @@ -106,6 +106,16 @@ SECTIONS
__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
} > SRAM1

.lwip :
{
. = ALIGN(8);
__lwip_bss_start__ = .;
*mbed-os/features/lwipstack*.o(.bss*)
*mbed-os/features/lwipstack*.o(COMMON)
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I don't think LWIP is a defaut feature on all L475 based boards - will that work fine anyway when there are no LWIP symbols at all (mbed2 application for instance)

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Should work, I tested this precise use case by disabling lwip. I saw no ill effects. Can't comment for mbed2, though.

. = ALIGN(8);
__lwip_bss_end__ = .;
} > SRAM1

.data : AT (__etext)
{
__data_start__ = .;
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12 changes: 12 additions & 0 deletions ...RGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l475xx.S
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Expand Up @@ -93,6 +93,18 @@ LoopCopyDataInit:
cmp r2, r3
bcc CopyDataInit

/* Zero LWIP .bss section in second RAM region */
ldr r1, =__lwip_bss_start__
ldr r2, =__lwip_bss_end__

movs r0, 0

LWIPBssInit:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt LWIPBssInit

/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
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6 changes: 3 additions & 3 deletions targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf
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Expand Up @@ -33,15 +33,15 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
}

define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
define symbol __size_heap__ = 0x17000;
define symbol __size_heap__ = 0x13C00;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block HEAP with expanding size, minimum size = __size_heap__, alignment = 8 { };

initialize by copy with packing = zeros { readwrite };
do not initialize { section .noinit };

place at address mem:__intvec_start__ { readonly section .intvec };

place in ROM_region { readonly };
place in SRAM1_region { readwrite, block HEAP };
place in SRAM1_region { readwrite, zeroinit object *lwip*.o, block HEAP };
place in SRAM2_region { first block CSTACK, zeroinit };