Skip to content

Commit 116d334

Browse files
ArchcadyArchcady
committed
add ARMmbed#3995 (tools/targets/)
1 parent 8fb8fe7 commit 116d334

File tree

5 files changed

+269
-20
lines changed

5 files changed

+269
-20
lines changed

‎tools/build_hooks/__init__.py

Lines changed: 0 additions & 16 deletions
This file was deleted.

‎tools/targets/LPC.py

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
"""
2+
mbed SDK
3+
Copyright (c) 2011-2013 ARM Limited
4+
5+
Licensed under the Apache License, Version 2.0 (the "License");
6+
you may not use this file except in compliance with the License.
7+
You may obtain a copy of the License at
8+
9+
http://www.apache.org/licenses/LICENSE-2.0
10+
11+
Unless required by applicable law or agreed to in writing, software
12+
distributed under the License is distributed on an "AS IS" BASIS,
13+
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
See the License for the specific language governing permissions and
15+
limitations under the License.
16+
17+
18+
http://www.nxp.com/documents/user_manual/UM10360.pdf
19+
20+
32.3.1.1 Criterion for Valid User Code
21+
The reserved Cortex-M3 exception vector location 7 (offset 0x1C in the vector table)
22+
should contain the 2's complement of the check-sum of table entries 0 through 6. This
23+
causes the checksum of the first 8 table entries to be 0. The boot loader code checksums
24+
the first 8 locations in sector 0 of the flash. If the result is 0, then execution control is
25+
transferred to the user code.
26+
"""
27+
from struct import unpack, pack
28+
29+
30+
def patch(bin_path):
31+
with open(bin_path, 'r+b') as bin:
32+
# Read entries 0 through 6 (Little Endian 32bits words)
33+
vector = [unpack('<I', bin.read(4))[0] for _ in range(7)]
34+
35+
# location 7 (offset 0x1C in the vector table) should contain the 2's
36+
# complement of the check-sum of table entries 0 through 6
37+
bin.seek(0x1C)
38+
bin.write(pack('<I', (~sum(vector) + 1) & 0xFFFFFFFF))
39+
40+
41+
def is_patched(bin_path):
42+
with open(bin_path, 'rb') as bin:
43+
# The checksum of the first 8 table entries should be 0
44+
return (sum([unpack('<I', bin.read(4))[0] for _ in range(8)]) & 0xFFFFFFFF) == 0
45+
46+
47+
if __name__ == '__main__':
48+
bin_path = "C:/Users/emimon01/releases/emilmont/build/test/LPC1768/ARM/MBED_A1/basic.bin"
49+
patch(bin_path)
50+
assert is_patched(bin_path), "The file is not patched"

‎tools/targets/NCS.py

Lines changed: 215 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,215 @@
1+
"""
2+
@copyright (c) 2012 ON Semiconductor. All rights reserved.
3+
ON Semiconductor is supplying this software for use with ON Semiconductor
4+
processor based microcontrollers only.
5+
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
6+
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
7+
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
8+
ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
9+
INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
10+
"""
11+
12+
from __future__ import absolute_import
13+
from __future__ import print_function
14+
15+
import itertools
16+
import binascii
17+
import intelhex
18+
from tools.config import Config
19+
20+
FIB_BASE = 0x2000
21+
FLASH_BASE = 0x3000
22+
FW_REV = 0x01000100
23+
TRIM_BASE = 0x2800
24+
25+
def ranges(i):
26+
for _, b in itertools.groupby(enumerate(i), lambda x_y: x_y[1] - x_y[0]):
27+
b = list(b)
28+
yield b[0][1], b[-1][1]
29+
30+
31+
def add_fib_at_start(arginput):
32+
input_file = arginput + ".bin"
33+
file_name_hex = arginput + "_fib.hex"
34+
file_name_bin = arginput + ".bin"
35+
36+
# Read in hex file
37+
input_hex_file = intelhex.IntelHex()
38+
input_hex_file.padding = 0x00
39+
input_hex_file.loadbin(input_file, offset=FLASH_BASE)
40+
41+
output_hex_file = intelhex.IntelHex()
42+
output_hex_file.padding = 0x00
43+
44+
# Get the starting and ending address
45+
addresses = input_hex_file.addresses()
46+
addresses.sort()
47+
start_end_pairs = list(ranges(addresses))
48+
regions = len(start_end_pairs)
49+
50+
if regions == 1:
51+
start, end = start_end_pairs[0]
52+
else:
53+
start = min(min(start_end_pairs))
54+
end = max(max(start_end_pairs))
55+
56+
assert start >= FLASH_BASE, ("Error - start 0x%x less than begining of user\
57+
flash area" %start)
58+
# Compute checksum over the range (don't include data at location of crc)
59+
size = end - start + 1
60+
data = input_hex_file.tobinarray(start=start, size=size)
61+
crc32 = binascii.crc32(data) & 0xFFFFFFFF
62+
63+
fw_rev = FW_REV
64+
65+
checksum = (start + size + crc32 + fw_rev) & 0xFFFFFFFF
66+
67+
print("Writing FIB: base 0x%08X, size 0x%08X, crc32 0x%08X, fw rev 0x%08X,\
68+
checksum 0x%08X" % (start, size, crc32, fw_rev, checksum))
69+
70+
#expected initial values used by daplink to validate that it is a valid bin
71+
#file added as dummy values in this file because the fib area preceeds the
72+
#application area the bootloader will ignore these dummy values
73+
# 00 is stack pointer (RAM address)
74+
# 04 is Reset vector (FLASH address)
75+
# 08 NMI_Handler (FLASH address)
76+
# 0C HardFault_Handler(FLASH address)
77+
# 10 dummy
78+
dummy_sp = 0x3FFFFC00
79+
dummy_reset_vector = 0x00003625
80+
dummy_nmi_handler = 0x00003761
81+
dummy_hardfault_handler = 0x00003691
82+
dummy_blank = 0x00000000
83+
84+
#expected fib structure
85+
#typedef struct fib{
86+
#uint32_t base; /**< Base offset of firmware, indicating what flash the
87+
# firmware is in. (will never be 0x11111111) */
88+
#uint32_t size; /**< Size of the firmware */
89+
#uint32_t crc; /**< CRC32 for firmware correctness check */
90+
#uint32_t rev; /**< Revision number */
91+
#uint32_t checksum; /**< Check-sum of information block */
92+
#}fib_t, *fib_pt;
93+
94+
fib_start = FIB_BASE
95+
dummy_fib_size = 20
96+
fib_size = 20
97+
trim_size = 24
98+
user_code_start = FLASH_BASE
99+
trim_area_start = TRIM_BASE
100+
101+
# Write FIB to the file in little endian
102+
output_hex_file[fib_start + 0] = (dummy_sp >> 0) & 0xFF
103+
output_hex_file[fib_start + 1] = (dummy_sp >> 8) & 0xFF
104+
output_hex_file[fib_start + 2] = (dummy_sp >> 16) & 0xFF
105+
output_hex_file[fib_start + 3] = (dummy_sp >> 24) & 0xFF
106+
107+
output_hex_file[fib_start + 4] = (dummy_reset_vector >> 0) & 0xFF
108+
output_hex_file[fib_start + 5] = (dummy_reset_vector >> 8) & 0xFF
109+
output_hex_file[fib_start + 6] = (dummy_reset_vector >> 16) & 0xFF
110+
output_hex_file[fib_start + 7] = (dummy_reset_vector >> 24) & 0xFF
111+
112+
output_hex_file[fib_start + 8] = (dummy_nmi_handler >> 0) & 0xFF
113+
output_hex_file[fib_start + 9] = (dummy_nmi_handler >> 8) & 0xFF
114+
output_hex_file[fib_start + 10] = (dummy_nmi_handler >> 16) & 0xFF
115+
output_hex_file[fib_start + 11] = (dummy_nmi_handler >> 24) & 0xFF
116+
117+
output_hex_file[fib_start + 12] = (dummy_hardfault_handler >> 0) & 0xFF
118+
output_hex_file[fib_start + 13] = (dummy_hardfault_handler >> 8) & 0xFF
119+
output_hex_file[fib_start + 14] = (dummy_hardfault_handler >> 16) & 0xFF
120+
output_hex_file[fib_start + 15] = (dummy_hardfault_handler >> 24) & 0xFF
121+
122+
output_hex_file[fib_start + 16] = (dummy_blank >> 0) & 0xFF
123+
output_hex_file[fib_start + 17] = (dummy_blank >> 8) & 0xFF
124+
output_hex_file[fib_start + 18] = (dummy_blank >> 16) & 0xFF
125+
output_hex_file[fib_start + 19] = (dummy_blank >> 24) & 0xFF
126+
127+
# Write FIB to the file in little endian
128+
output_hex_file[fib_start + 20] = (start >> 0) & 0xFF
129+
output_hex_file[fib_start + 21] = (start >> 8) & 0xFF
130+
output_hex_file[fib_start + 22] = (start >> 16) & 0xFF
131+
output_hex_file[fib_start + 23] = (start >> 24) & 0xFF
132+
133+
output_hex_file[fib_start + 24] = (size >> 0) & 0xFF
134+
output_hex_file[fib_start + 25] = (size >> 8) & 0xFF
135+
output_hex_file[fib_start + 26] = (size >> 16) & 0xFF
136+
output_hex_file[fib_start + 27] = (size >> 24) & 0xFF
137+
138+
output_hex_file[fib_start + 28] = (crc32 >> 0) & 0xFF
139+
output_hex_file[fib_start + 29] = (crc32 >> 8) & 0xFF
140+
output_hex_file[fib_start + 30] = (crc32 >> 16) & 0xFF
141+
output_hex_file[fib_start + 31] = (crc32 >> 24) & 0xFF
142+
143+
output_hex_file[fib_start + 32] = (fw_rev >> 0) & 0xFF
144+
output_hex_file[fib_start + 33] = (fw_rev >> 8) & 0xFF
145+
output_hex_file[fib_start + 34] = (fw_rev >> 16) & 0xFF
146+
output_hex_file[fib_start + 35] = (fw_rev >> 24) & 0xFF
147+
148+
output_hex_file[fib_start + 36] = (checksum >> 0) & 0xFF
149+
output_hex_file[fib_start + 37] = (checksum >> 8) & 0xFF
150+
output_hex_file[fib_start + 38] = (checksum >> 16) & 0xFF
151+
output_hex_file[fib_start + 39] = (checksum >> 24) & 0xFF
152+
153+
#pad the rest of the file
154+
for i in range(fib_start + dummy_fib_size + fib_size, trim_area_start):
155+
output_hex_file[i] = 0xFF
156+
157+
# Read in configuration data from the config parameter in targets.json
158+
configData = Config('NCS36510')
159+
paramData = configData.get_target_config_data()
160+
for v in paramData.values():
161+
if (v.name == "target.mac-addr-high"):
162+
mac_addr_high = int(v.value, 16)
163+
elif (v.name == "target.mac-addr-low"):
164+
mac_addr_low = int(v.value,16)
165+
elif (v.name == "target.32KHz-clk-trim"):
166+
clk_32k_trim = int(v.value,16)
167+
elif (v.name == "target.32MHz-clk-trim"):
168+
clk_32m_trim = int(v.value,16)
169+
elif (v.name == "target.rssi-trim"):
170+
rssi = int(v.value,16)
171+
elif (v.name == "target.txtune-trim"):
172+
txtune = int(v.value,16)
173+
else:
174+
print("Not a valid param")
175+
176+
output_hex_file[trim_area_start + 0] = mac_addr_low & 0xFF
177+
output_hex_file[trim_area_start + 1] = (mac_addr_low >> 8) & 0xFF
178+
output_hex_file[trim_area_start + 2] = (mac_addr_low >> 16) & 0xFF
179+
output_hex_file[trim_area_start + 3] = (mac_addr_low >> 24) & 0xFF
180+
181+
output_hex_file[trim_area_start + 4] = mac_addr_high & 0xFF
182+
output_hex_file[trim_area_start + 5] = (mac_addr_high >> 8) & 0xFF
183+
output_hex_file[trim_area_start + 6] = (mac_addr_high >> 16) & 0xFF
184+
output_hex_file[trim_area_start + 7] = (mac_addr_high >> 24) & 0xFF
185+
186+
output_hex_file[trim_area_start + 8] = clk_32k_trim & 0xFF
187+
output_hex_file[trim_area_start + 9] = (clk_32k_trim >> 8) & 0xFF
188+
output_hex_file[trim_area_start + 10] = (clk_32k_trim >> 16) & 0xFF
189+
output_hex_file[trim_area_start + 11] = (clk_32k_trim >> 24) & 0xFF
190+
191+
output_hex_file[trim_area_start + 12] = clk_32m_trim & 0xFF
192+
output_hex_file[trim_area_start + 13] = (clk_32m_trim >> 8) & 0xFF
193+
output_hex_file[trim_area_start + 14] = (clk_32m_trim >> 16) & 0xFF
194+
output_hex_file[trim_area_start + 15] = (clk_32m_trim >> 24) & 0xFF
195+
196+
output_hex_file[trim_area_start + 16] = rssi & 0xFF
197+
output_hex_file[trim_area_start + 17] = (rssi >> 8) & 0xFF
198+
output_hex_file[trim_area_start + 18] = (rssi >> 16) & 0xFF
199+
output_hex_file[trim_area_start + 19] = (rssi >> 24) & 0xFF
200+
201+
output_hex_file[trim_area_start + 20] = txtune & 0xFF
202+
output_hex_file[trim_area_start + 21] = (txtune >> 8) & 0xFF
203+
output_hex_file[trim_area_start + 22] = (txtune >> 16) & 0xFF
204+
output_hex_file[trim_area_start + 23] = (txtune >> 24) & 0xFF
205+
206+
# pad the rest of the area with 0xFF
207+
for i in range(trim_area_start + trim_size, user_code_start):
208+
output_hex_file[i] = 0xFF
209+
210+
#merge two hex files
211+
output_hex_file.merge(input_hex_file, overlap='error')
212+
213+
# Write out file(s)
214+
output_hex_file.tofile(file_name_hex, 'hex')
215+
output_hex_file.tofile(file_name_bin, 'bin')

‎tools/build_hooks/REALTEK_RTL8195AM.py renamed to ‎tools/targets/REALTEK_RTL8195AM.py

File renamed without changes.

‎tools/targets.py renamed to ‎tools/targets/__init__.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
import sys
2424
from copy import copy
2525
from collections import namedtuple
26-
from tools.patch import patch
26+
from tools.targets.LPC import patch
2727
from tools.paths import TOOLS_BOOTLOADERS
2828
from tools.utils import json_file_to_dict
2929

@@ -121,7 +121,7 @@ class Target(namedtuple("Target", "name json_data resolution_order resolution_or
121121

122122
# Default location of the 'targets.json' file
123123
__targets_json_location_default = os.path.join(
124-
os.path.dirname(os.path.abspath(__file__)), '..', 'targets', 'targets.json')
124+
os.path.dirname(os.path.abspath(__file__)), '..', '..', 'targets', 'targets.json')
125125

126126
# Current/new location of the 'targets.json' file
127127
__targets_json_location = None
@@ -494,15 +494,15 @@ def binary_hook(t_self, resources, _, binf):
494494
class NCS36510TargetCode:
495495
@staticmethod
496496
def ncs36510_addfib(t_self, resources, elf, binf):
497-
from tools.add_fib import add_fib_at_start
497+
from tools.targets.NCS import add_fib_at_start
498498
print("binf ", binf)
499499
add_fib_at_start(binf[:-4])
500500

501501
class RTL8195ACode:
502502
"""RTL8195A Hooks"""
503503
@staticmethod
504504
def binary_hook(t_self, resources, elf, binf):
505-
from tools.build_hooks.REALTEK_RTL8195AM import rtl8195a_elf2bin
505+
from tools.targets.REALTEK_RTL8195AM import rtl8195a_elf2bin
506506
rtl8195a_elf2bin(t_self.name, elf, binf)
507507
################################################################################
508508

0 commit comments

Comments
 (0)