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Merged main:096eba148df7 into amd-gfx:402b76f9f567
Local branch amd-gfx 402b76f Merged main:4434253f0fa6 into amd-gfx:7f370063677b Remote branch main 096eba1 [TargetParser][AMDGPU] Fix getArchEntry(). (llvm#69222)
2 parents 402b76f + 096eba1 commit ca63cea

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10 files changed

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-50
lines changed

10 files changed

+37
-50
lines changed

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 477759
19+
#define LLVM_MAIN_REVISION 477764
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1200,9 +1200,9 @@ class AMDGPUStructPtrBufferStore<LLVMType data_ty = llvm_any_ty> : DefaultAttrsI
12001200
def int_amdgcn_struct_ptr_buffer_store_format : AMDGPUStructPtrBufferStore;
12011201
def int_amdgcn_struct_ptr_buffer_store : AMDGPUStructPtrBufferStore;
12021202

1203-
class AMDGPURawBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic <
1204-
!if(NoRtn, [], [data_ty]),
1205-
[!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR)
1203+
class AMDGPURawBufferAtomic<LLVMType data_ty = llvm_any_ty> : Intrinsic <
1204+
[data_ty],
1205+
[LLVMMatchType<0>, // vdata(VGPR)
12061206
llvm_v4i32_ty, // rsrc(SGPR)
12071207
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
12081208
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
@@ -1234,9 +1234,9 @@ def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic<
12341234
[ImmArg<ArgIndex<5>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
12351235
AMDGPURsrcIntrinsic<2, 0>;
12361236

1237-
class AMDGPURawPtrBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic <
1238-
!if(NoRtn, [], [data_ty]),
1239-
[!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR)
1237+
class AMDGPURawPtrBufferAtomic<LLVMType data_ty = llvm_any_ty> : Intrinsic <
1238+
[data_ty],
1239+
[LLVMMatchType<0>, // vdata(VGPR)
12401240
AMDGPUBufferRsrcTy, // rsrc(SGPR)
12411241
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
12421242
llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
@@ -1275,9 +1275,9 @@ def int_amdgcn_raw_ptr_buffer_atomic_cmpswap : Intrinsic<
12751275
def int_amdgcn_raw_buffer_atomic_fadd : AMDGPURawBufferAtomic<llvm_anyfloat_ty>;
12761276
def int_amdgcn_raw_ptr_buffer_atomic_fadd : AMDGPURawPtrBufferAtomic<llvm_anyfloat_ty>;
12771277

1278-
class AMDGPUStructBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic <
1279-
!if(NoRtn, [], [data_ty]),
1280-
[!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR)
1278+
class AMDGPUStructBufferAtomic<LLVMType data_ty = llvm_any_ty> : Intrinsic <
1279+
[data_ty],
1280+
[LLVMMatchType<0>, // vdata(VGPR)
12811281
llvm_v4i32_ty, // rsrc(SGPR)
12821282
llvm_i32_ty, // vindex(VGPR)
12831283
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
@@ -1309,9 +1309,9 @@ def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic<
13091309
[ImmArg<ArgIndex<6>>, IntrWillReturn, IntrNoCallback, IntrNoFree], "", [SDNPMemOperand]>,
13101310
AMDGPURsrcIntrinsic<2, 0>;
13111311

1312-
class AMDGPUStructPtrBufferAtomic<LLVMType data_ty = llvm_any_ty, bit NoRtn = false> : Intrinsic <
1313-
!if(NoRtn, [], [data_ty]),
1314-
[!if(NoRtn, data_ty, LLVMMatchType<0>), // vdata(VGPR)
1312+
class AMDGPUStructPtrBufferAtomic<LLVMType data_ty = llvm_any_ty> : Intrinsic <
1313+
[data_ty],
1314+
[LLVMMatchType<0>, // vdata(VGPR)
13151315
AMDGPUBufferRsrcTy, // rsrc(SGPR)
13161316
llvm_i32_ty, // vindex(VGPR)
13171317
llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -125,11 +125,11 @@ def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
125125

126126
def i1imm_0 : OperandWithDefaultOps<i1, (ops (i1 0))>;
127127

128-
class CustomOperandClass<string name, bit optional, string parserMethod,
129-
string defaultMethod>
128+
class CustomOperandClass<string name, bit optional, string predicateMethod,
129+
string parserMethod, string defaultMethod>
130130
: AsmOperandClass {
131131
let Name = name;
132-
let PredicateMethod = "is"#name;
132+
let PredicateMethod = predicateMethod;
133133
let ParserMethod = parserMethod;
134134
let RenderMethod = "addImmOperands";
135135
let IsOptional = optional;
@@ -138,14 +138,16 @@ class CustomOperandClass<string name, bit optional, string parserMethod,
138138

139139
class CustomOperandProps<bit optional = 0, string name = NAME> {
140140
string ImmTy = "ImmTy"#name;
141+
string PredicateMethod = "is"#name;
141142
string ParserMethod = "parse"#name;
142143
string DefaultValue = "0";
143144
string DefaultMethod = "[this]() { return "#
144145
"AMDGPUOperand::CreateImm(this, "#DefaultValue#", SMLoc(), "#
145146
"AMDGPUOperand::"#ImmTy#"); }";
146147
string PrintMethod = "print"#name;
147148
AsmOperandClass ParserMatchClass =
148-
CustomOperandClass<name, optional, ParserMethod, DefaultMethod>;
149+
CustomOperandClass<name, optional, PredicateMethod, ParserMethod,
150+
DefaultMethod>;
149151
string OperandType = "OPERAND_IMMEDIATE";
150152
}
151153

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 9 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5879,31 +5879,23 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI,
58795879
IID == Intrinsic::amdgcn_struct_buffer_atomic_cmpswap ||
58805880
IID == Intrinsic::amdgcn_raw_ptr_buffer_atomic_cmpswap ||
58815881
IID == Intrinsic::amdgcn_struct_ptr_buffer_atomic_cmpswap;
5882-
const bool HasReturn = MI.getNumExplicitDefs() != 0;
5883-
5884-
Register Dst;
5885-
5886-
int OpOffset = 0;
5887-
if (HasReturn) {
5888-
// A few FP atomics do not support return values.
5889-
Dst = MI.getOperand(0).getReg();
5890-
} else {
5891-
OpOffset = -1;
5892-
}
58935882

5883+
Register Dst = MI.getOperand(0).getReg();
58945884
// Since we don't have 128-bit atomics, we don't need to handle the case of
58955885
// p8 argmunents to the atomic itself
5896-
Register VData = MI.getOperand(2 + OpOffset).getReg();
5886+
Register VData = MI.getOperand(2).getReg();
5887+
58975888
Register CmpVal;
5889+
int OpOffset = 0;
58985890

58995891
if (IsCmpSwap) {
5900-
CmpVal = MI.getOperand(3 + OpOffset).getReg();
5892+
CmpVal = MI.getOperand(3).getReg();
59015893
++OpOffset;
59025894
}
59035895

59045896
castBufferRsrcArgToV4I32(MI, B, 3 + OpOffset);
59055897
Register RSrc = MI.getOperand(3 + OpOffset).getReg();
5906-
const unsigned NumVIndexOps = (IsCmpSwap ? 8 : 7) + HasReturn;
5898+
const unsigned NumVIndexOps = IsCmpSwap ? 9 : 8;
59075899

59085900
// The struct intrinsic variants add one additional operand over raw.
59095901
const bool HasVIndex = MI.getNumOperands() == NumVIndexOps;
@@ -5924,12 +5916,9 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI,
59245916
unsigned ImmOffset;
59255917
std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset);
59265918

5927-
auto MIB = B.buildInstr(getBufferAtomicPseudo(IID));
5928-
5929-
if (HasReturn)
5930-
MIB.addDef(Dst);
5931-
5932-
MIB.addUse(VData); // vdata
5919+
auto MIB = B.buildInstr(getBufferAtomicPseudo(IID))
5920+
.addDef(Dst)
5921+
.addUse(VData); // vdata
59335922

59345923
if (IsCmpSwap)
59355924
MIB.addReg(CmpVal);

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -356,25 +356,20 @@ class AMDGPUOperand : public MCParsedAsmOperand {
356356
return isImm() && Imm.Type == ImmT;
357357
}
358358

359+
template <ImmTy Ty> bool isImmTy() const { return isImmTy(Ty); }
360+
359361
bool isImmLiteral() const { return isImmTy(ImmTyNone); }
360362

361363
bool isImmModifier() const {
362364
return isImm() && Imm.Type != ImmTyNone;
363365
}
364366

365-
bool isClampSI() const { return isImmTy(ImmTyClampSI); }
366367
bool isOModSI() const { return isImmTy(ImmTyOModSI); }
367368
bool isDMask() const { return isImmTy(ImmTyDMask); }
368369
bool isDim() const { return isImmTy(ImmTyDim); }
369-
bool isUNorm() const { return isImmTy(ImmTyUNorm); }
370-
bool isDA() const { return isImmTy(ImmTyDA); }
371370
bool isR128A16() const { return isImmTy(ImmTyR128A16); }
372-
bool isA16() const { return isImmTy(ImmTyA16); }
373-
bool isLWE() const { return isImmTy(ImmTyLWE); }
374371
bool isOff() const { return isImmTy(ImmTyOff); }
375372
bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
376-
bool isExpVM() const { return isImmTy(ImmTyExpVM); }
377-
bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
378373
bool isOffen() const { return isImmTy(ImmTyOffen); }
379374
bool isIdxen() const { return isImmTy(ImmTyIdxen); }
380375
bool isAddr64() const { return isImmTy(ImmTyAddr64); }
@@ -387,7 +382,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
387382
bool isLDS() const { return isImmTy(ImmTyLDS); }
388383
bool isCPol() const { return isImmTy(ImmTyCPol); }
389384
bool isTFE() const { return isImmTy(ImmTyTFE); }
390-
bool isD16() const { return isImmTy(ImmTyD16); }
391385
bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }
392386
bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }
393387
bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }
@@ -404,7 +398,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
404398
bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
405399
bool isNegLo() const { return isImmTy(ImmTyNegLo); }
406400
bool isNegHi() const { return isImmTy(ImmTyNegHi); }
407-
bool isHigh() const { return isImmTy(ImmTyHigh); }
408401

409402
bool isRegOrImm() const {
410403
return isReg() || isImm();

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1045,6 +1045,7 @@ class NamedIntOperand<ValueType Type, string Prefix, string Name = NAME,
10451045

10461046
class NamedBitOperand<string Id, string Name = NAME>
10471047
: CustomOperand<i1, 1, Name> {
1048+
let PredicateMethod = "isImmTy<AMDGPUOperand::"#ImmTy#">";
10481049
let ParserMethod =
10491050
"[this](OperandVector &Operands) -> ParseStatus { "#
10501051
"return parseNamedBit(\""#Id#"\", Operands, AMDGPUOperand::"#ImmTy#"); }";
@@ -1056,6 +1057,7 @@ class NamedBitOperand<string Id, string Name = NAME>
10561057
class DefaultOperand<CustomOperand Op, int Value>
10571058
: OperandWithDefaultOps<Op.Type, (ops (Op.Type Value))>,
10581059
CustomOperandProps<1, Op.ParserMatchClass.Name> {
1060+
let PredicateMethod = Op.ParserMatchClass.PredicateMethod;
10591061
let ParserMethod = Op.ParserMatchClass.ParserMethod;
10601062
let PrintMethod = Op.PrintMethod;
10611063
}

‎llvm/lib/Target/AMDGPU/SIInstructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3665,8 +3665,8 @@ def G_AMDGPU_ATOMIC_FMIN : G_ATOMICRMW_OP;
36653665
def G_AMDGPU_ATOMIC_FMAX : G_ATOMICRMW_OP;
36663666
}
36673667

3668-
class BufferAtomicGenericInstruction<bit NoRtn = 0> : AMDGPUGenericInstruction {
3669-
let OutOperandList = !if(NoRtn, (outs), (outs type0:$dst));
3668+
class BufferAtomicGenericInstruction : AMDGPUGenericInstruction {
3669+
let OutOperandList = (outs type0:$dst);
36703670
let InOperandList = (ins type0:$vdata, type1:$rsrc, type2:$vindex, type2:$voffset,
36713671
type2:$soffset, untyped_imm_0:$offset,
36723672
untyped_imm_0:$cachepolicy, untyped_imm_0:$idxen);

‎llvm/lib/TargetParser/TargetParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ const GPUInfo *getArchEntry(AMDGPU::GPUKind AK, ArrayRef<GPUInfo> Table) {
133133
return A.Kind < B.Kind;
134134
});
135135

136-
if (I == Table.end())
136+
if (I == Table.end() || I->Kind != Search.Kind)
137137
return nullptr;
138138
return I;
139139
}

‎utils/bazel/llvm-project-overlay/clang/BUILD.bazel

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1860,6 +1860,7 @@ cc_library(
18601860
"//llvm:IRReader",
18611861
"//llvm:InstCombine",
18621862
"//llvm:Instrumentation",
1863+
"//llvm:HipStdPar",
18631864
"//llvm:LTO",
18641865
"//llvm:Linker",
18651866
"//llvm:MC",

‎utils/bazel/llvm-project-overlay/mlir/test/Dialect/BUILD.bazel

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ package(default_visibility = ["//visibility:public"])
3535
"Transform/*-symbol-decl-and-schedule.mlir",
3636
"Transform/*-symbol-decl-dir.mlir",
3737
"Transform/*-symbol-decl-invalid.mlir",
38-
"Transform/Library/*.mlir"
38+
"Transform/Library/*.mlir",
3939
"Transform/preload-library.mlir",
4040
"Transform/test-interpreter-library/*.mlir",
4141
"Transform/test-repro-dump.mlir",

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