Merged main:c0722478d5c1 into amd-gfx:94e1716d2b22

Local branch amd-gfx 94e1716 Merged main:ea81e31aa11c into amd-gfx:376ca00d5225
Remote branch main c072247 [lld][ELF] Add getBitcodeMachineKind test for LoongArch (llvm#71931)

Author: SC llvm team

lld/test/ELF/lto/loongarch.ll

@@ -0,0 +1,32 @@
+; REQUIRES: loongarch
+;; Test we can infer the e_machine value EM_LOONGARCH from a bitcode file.
+
+; RUN: split-file %s %t
+; RUN: llvm-as %t/32.ll -o %t/32.o
+; RUN: ld.lld %t/32.o -o %t/32
+; RUN: llvm-readobj -h %t/32 | FileCheck %s --check-prefixes=CHECK,LA32
+
+; RUN: llvm-as %t/64.ll -o %t/64.o
+; RUN: ld.lld %t/64.o -o %t/64
+; RUN: llvm-readobj -h %t/64 | FileCheck %s --check-prefixes=CHECK,LA64
+
+; LA32:    Class: 32-bit
+; LA64:    Class: 64-bit
+; CHECK:   DataEncoding: LittleEndian
+; CHECK: Machine: EM_LOONGARCH
+
+;--- 32.ll
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "loongarch32-unknown-elf"
+
+define void @_start() {
+  ret void
+}
+
+;--- 64.ll
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "loongarch64-unknown-elf"
+
+define void @_start() {
+  ret void
+}

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 481626
+#define LLVM_MAIN_REVISION 481630
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

@@ -549,11 +549,7 @@ enum : uint64_t {
   /// byte to specify a destination which in this case is memory and operand 3
   /// with VEX.VVVV, and also encodes a condition code.
   MRMDestMem4VOp3CC = 20,
-  /// MRM[0-7][rm] - These forms are used to represent instructions that use
-  /// a Mod/RM byte, and use the middle field to hold extended opcode
-  /// information.  In the intel manual these are represented as /0, /1, ...
-  ///
-  // Instructions operate on a register Reg/Opcode operand not the r/m field.
+  /// Instructions operate on a register Reg/Opcode operand not the r/m field.
   MRMr0 = 21,
   /// MRMSrcMem - But force to use the SIB field.
   MRMSrcMemFSIB = 22,
@@ -581,7 +577,8 @@ enum : uint64_t {
   /// MRMXm - This form is used for instructions that use the Mod/RM byte
   /// to specify a memory source, but doesn't use the middle field.
   MRMXm = 31,
-  /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand.
+  /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use
+  /// reg field to hold extended opcode, which is represented as /0, /1, ...
   MRM0m = 32, // Format /0
   MRM1m = 33, // Format /1
   MRM2m = 34, // Format /2
@@ -612,7 +609,8 @@ enum : uint64_t {
   /// MRMXr - This form is used for instructions that use the Mod/RM byte
   /// to specify a register source, but doesn't use the middle field.
   MRMXr = 47,
-  /// MRM0r-MRM7r - Instructions that operate on a register r/m operand.
+  /// MRM0r-MRM7r - Instructions that operate on a register r/m operand and use
+  /// reg field to hold extended opcode, which is represented as /0, /1, ...
   MRM0r = 48, // Format /0
   MRM1r = 49, // Format /1
   MRM2r = 50, // Format /2