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Fix step number references in ARM64 exception handling #5114

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Nov 1, 2024
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Fix step number references in ARM64 exception handling #5114

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2 changes: 1 addition & 1 deletion docs/build/arm64-exception-handling.md
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Original file line number Diff line number Diff line change
Expand Up @@ -393,7 +393,7 @@ Step 6: Allocate remaining stack, including local area, `<x29,lr>` pair, and out
| 6d | (**CR** == 00 \|\| **CR** == 01) &&<br/>`#locsz` <= 4080 | 1 | `sub sp,sp,#locsz` | `alloc_s`/`alloc_m` |
| 6e | (**CR** == 00 \|\| **CR** == 01) &&<br/>`#locsz` > 4080 | 2 | `sub sp,sp,4080`<br/>`sub sp,sp,#(locsz-4080)` | `alloc_m`<br/>`alloc_s`/`alloc_m` |

\* If **CR** == 01 and **RegI** is an odd number, Step 2 and the last `save_rep` in step 1 are merged into one `save_regp`.
\* If **CR** == 01 and **RegI** is an odd number, step 3 and the last `save_reg` in step 2 are merged into one `save_regp`.
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@mstorsjo, thank you for the updates. I'm still a little confused. There is no save_reg in step 2. There's a save_regp.

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Understandable - it's not spelled out in too much detail.

In step 2, we have one save_regp_x followed by more save_regp - for each pair of registers that are backed up. If the number of registers is odd, the last one is save_reg, not save_regp, as the last one doesn't have a pair.

And for that case - if the last one is a lone register, when RegI is odd, the save of LR from step 3 (which also would have been a save_reg) is merged into a paired store of registers into save_regp.


\*\* If **RegI** == **CR** == 0, and **RegF** != 0, the first `stp` for the floating-point does the predecrement.

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