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[AMDGPU][CodeGen] Support raw format TFE buffer loads other than byte, short and d16 ones.
Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138215
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2 files changed

+8
-4
lines changed

2 files changed

+8
-4
lines changed

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4548,19 +4548,22 @@ bool AMDGPULegalizerInfo::legalizeBufferLoad(MachineInstr &MI,
45484548

45494549
// TODO: Support TFE for typed and narrow loads.
45504550
if (IsTyped) {
4551-
assert(!IsTFE);
4551+
if (IsTFE)
4552+
return false;
45524553
Opc = IsD16 ? AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16 :
45534554
AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT;
45544555
} else if (IsFormat) {
45554556
if (IsD16) {
4556-
assert(!IsTFE);
4557+
if (IsTFE)
4558+
return false;
45574559
Opc = AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16;
45584560
} else {
45594561
Opc = IsTFE ? AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE
45604562
: AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT;
45614563
}
45624564
} else {
4563-
assert(!IsTFE);
4565+
if (IsTFE)
4566+
return false;
45644567
switch (MemTy.getSizeInBits()) {
45654568
case 8:
45664569
Opc = AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE;

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4894,7 +4894,8 @@ SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
48944894
: AMDGPUISD::BUFFER_LOAD_FORMAT;
48954895
} else {
48964896
// TODO: Support non-format TFE loads.
4897-
assert(!IsTFE);
4897+
if (IsTFE)
4898+
return SDValue();
48984899
Opc = AMDGPUISD::BUFFER_LOAD;
48994900
}
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