@@ -587,7 +587,7 @@ static int max310x_update_best_err(unsigned long f, long *besterr)
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return 1 ;
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}
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- static u32 max310x_set_ref_clk (struct device * dev , struct max310x_port * s ,
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+ static s32 max310x_set_ref_clk (struct device * dev , struct max310x_port * s ,
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unsigned long freq , bool xtal )
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{
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unsigned int div , clksrc , pllcfg = 0 ;
@@ -657,7 +657,8 @@ static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s,
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} while (!stable && (++ try < MAX310X_XTAL_WAIT_RETRIES ));
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if (!stable )
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- dev_warn (dev , "clock is not stable yet\n" );
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+ return dev_err_probe (dev , - EAGAIN ,
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+ "clock is not stable\n" );
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}
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return bestfreq ;
@@ -1282,7 +1283,7 @@ static int max310x_probe(struct device *dev, const struct max310x_devtype *devty
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{
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int i , ret , fmin , fmax , freq ;
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struct max310x_port * s ;
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- u32 uartclk = 0 ;
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+ s32 uartclk = 0 ;
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bool xtal ;
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for (i = 0 ; i < devtype -> nr ; i ++ )
@@ -1360,6 +1361,11 @@ static int max310x_probe(struct device *dev, const struct max310x_devtype *devty
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}
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uartclk = max310x_set_ref_clk (dev , s , freq , xtal );
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+ if (uartclk < 0 ) {
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+ ret = uartclk ;
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+ goto out_uart ;
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+ }
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+
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dev_dbg (dev , "Reference clock set to %i Hz\n" , uartclk );
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for (i = 0 ; i < devtype -> nr ; i ++ ) {
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