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drm/msm/dpu: inline IRQ_n_MASK defines
IRQ masks are rarely shared between different DPU revisions. Inline them to the dpu_mdss_cfg intances and drop them from the dpu_hw_catalog.c Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/530875/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
1 parent d16b77d commit e5edf65

14 files changed

+99
-86
lines changed

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,14 @@ static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
197197
.vbif = msm8998_vbif,
198198
.reg_dma_count = 0,
199199
.perf = &msm8998_perf_data,
200-
.mdss_irqs = IRQ_SM8250_MASK,
200+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
201+
BIT(MDP_SSPP_TOP0_INTR2) | \
202+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
203+
BIT(MDP_INTF0_INTR) | \
204+
BIT(MDP_INTF1_INTR) | \
205+
BIT(MDP_INTF2_INTR) | \
206+
BIT(MDP_INTF3_INTR) | \
207+
BIT(MDP_INTF4_INTR),
201208
};
202209

203210
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -196,7 +196,15 @@ static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
196196
.reg_dma_count = 1,
197197
.dma_cfg = &sdm845_regdma,
198198
.perf = &sdm845_perf_data,
199-
.mdss_irqs = IRQ_SDM845_MASK,
199+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
200+
BIT(MDP_SSPP_TOP0_INTR2) | \
201+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
202+
BIT(MDP_INTF0_INTR) | \
203+
BIT(MDP_INTF1_INTR) | \
204+
BIT(MDP_INTF2_INTR) | \
205+
BIT(MDP_INTF3_INTR) | \
206+
BIT(MDP_AD4_0_INTR) | \
207+
BIT(MDP_AD4_1_INTR),
200208
};
201209

202210
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -223,7 +223,15 @@ static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
223223
.reg_dma_count = 1,
224224
.dma_cfg = &sm8150_regdma,
225225
.perf = &sm8150_perf_data,
226-
.mdss_irqs = IRQ_SDM845_MASK,
226+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
227+
BIT(MDP_SSPP_TOP0_INTR2) | \
228+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
229+
BIT(MDP_INTF0_INTR) | \
230+
BIT(MDP_INTF1_INTR) | \
231+
BIT(MDP_INTF2_INTR) | \
232+
BIT(MDP_INTF3_INTR) | \
233+
BIT(MDP_AD4_0_INTR) | \
234+
BIT(MDP_AD4_1_INTR),
227235
};
228236

229237
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,17 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
201201
.reg_dma_count = 1,
202202
.dma_cfg = &sm8150_regdma,
203203
.perf = &sc8180x_perf_data,
204-
.mdss_irqs = IRQ_SC8180X_MASK,
204+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
205+
BIT(MDP_SSPP_TOP0_INTR2) | \
206+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
207+
BIT(MDP_INTF0_INTR) | \
208+
BIT(MDP_INTF1_INTR) | \
209+
BIT(MDP_INTF2_INTR) | \
210+
BIT(MDP_INTF3_INTR) | \
211+
BIT(MDP_INTF4_INTR) | \
212+
BIT(MDP_INTF5_INTR) | \
213+
BIT(MDP_AD4_0_INTR) | \
214+
BIT(MDP_AD4_1_INTR),
205215
};
206216

207217
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -231,7 +231,14 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
231231
.reg_dma_count = 1,
232232
.dma_cfg = &sm8250_regdma,
233233
.perf = &sm8250_perf_data,
234-
.mdss_irqs = IRQ_SM8250_MASK,
234+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
235+
BIT(MDP_SSPP_TOP0_INTR2) | \
236+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
237+
BIT(MDP_INTF0_INTR) | \
238+
BIT(MDP_INTF1_INTR) | \
239+
BIT(MDP_INTF2_INTR) | \
240+
BIT(MDP_INTF3_INTR) | \
241+
BIT(MDP_INTF4_INTR),
235242
};
236243

237244
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -146,7 +146,11 @@ static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
146146
.reg_dma_count = 1,
147147
.dma_cfg = &sdm845_regdma,
148148
.perf = &sc7180_perf_data,
149-
.mdss_irqs = IRQ_SC7180_MASK,
149+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
150+
BIT(MDP_SSPP_TOP0_INTR2) | \
151+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
152+
BIT(MDP_INTF0_INTR) | \
153+
BIT(MDP_INTF1_INTR),
150154
};
151155

152156
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,11 @@ static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
119119
.vbif_count = ARRAY_SIZE(sdm845_vbif),
120120
.vbif = sdm845_vbif,
121121
.perf = &sm6115_perf_data,
122-
.mdss_irqs = IRQ_SC7180_MASK,
122+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
123+
BIT(MDP_SSPP_TOP0_INTR2) | \
124+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
125+
BIT(MDP_INTF0_INTR) | \
126+
BIT(MDP_INTF1_INTR),
123127
};
124128

125129
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,11 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
109109
.vbif_count = ARRAY_SIZE(sdm845_vbif),
110110
.vbif = sdm845_vbif,
111111
.perf = &qcm2290_perf_data,
112-
.mdss_irqs = IRQ_SC7180_MASK,
112+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
113+
BIT(MDP_SSPP_TOP0_INTR2) | \
114+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
115+
BIT(MDP_INTF0_INTR) | \
116+
BIT(MDP_INTF1_INTR),
113117
};
114118

115119
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -214,7 +214,13 @@ static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
214214
.reg_dma_count = 1,
215215
.dma_cfg = &sm8350_regdma,
216216
.perf = &sm8350_perf_data,
217-
.mdss_irqs = IRQ_SM8350_MASK,
217+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
218+
BIT(MDP_SSPP_TOP0_INTR2) | \
219+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
220+
BIT(MDP_INTF0_7xxx_INTR) | \
221+
BIT(MDP_INTF1_7xxx_INTR) | \
222+
BIT(MDP_INTF2_7xxx_INTR) | \
223+
BIT(MDP_INTF3_7xxx_INTR),
218224
};
219225

220226
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,12 @@ static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
147147
.vbif_count = ARRAY_SIZE(sdm845_vbif),
148148
.vbif = sdm845_vbif,
149149
.perf = &sc7280_perf_data,
150-
.mdss_irqs = IRQ_SC7280_MASK,
150+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
151+
BIT(MDP_SSPP_TOP0_INTR2) | \
152+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
153+
BIT(MDP_INTF0_7xxx_INTR) | \
154+
BIT(MDP_INTF1_7xxx_INTR) | \
155+
BIT(MDP_INTF5_7xxx_INTR),
151156
};
152157

153158
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -205,7 +205,18 @@ static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
205205
.reg_dma_count = 1,
206206
.dma_cfg = &sc8280xp_regdma,
207207
.perf = &sc8280xp_perf_data,
208-
.mdss_irqs = IRQ_SC8280XP_MASK,
208+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
209+
BIT(MDP_SSPP_TOP0_INTR2) | \
210+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
211+
BIT(MDP_INTF0_7xxx_INTR) | \
212+
BIT(MDP_INTF1_7xxx_INTR) | \
213+
BIT(MDP_INTF2_7xxx_INTR) | \
214+
BIT(MDP_INTF3_7xxx_INTR) | \
215+
BIT(MDP_INTF4_7xxx_INTR) | \
216+
BIT(MDP_INTF5_7xxx_INTR) | \
217+
BIT(MDP_INTF6_7xxx_INTR) | \
218+
BIT(MDP_INTF7_7xxx_INTR) | \
219+
BIT(MDP_INTF8_7xxx_INTR),
209220
};
210221

211222
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,13 @@ static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
222222
.reg_dma_count = 1,
223223
.dma_cfg = &sm8450_regdma,
224224
.perf = &sm8450_perf_data,
225-
.mdss_irqs = IRQ_SM8450_MASK,
225+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
226+
BIT(MDP_SSPP_TOP0_INTR2) | \
227+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
228+
BIT(MDP_INTF0_7xxx_INTR) | \
229+
BIT(MDP_INTF1_7xxx_INTR) | \
230+
BIT(MDP_INTF2_7xxx_INTR) | \
231+
BIT(MDP_INTF3_7xxx_INTR),
226232
};
227233

228234
#endif

‎drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,7 +227,13 @@ static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
227227
.reg_dma_count = 1,
228228
.dma_cfg = &sm8450_regdma,
229229
.perf = &sm8550_perf_data,
230-
.mdss_irqs = IRQ_SM8450_MASK,
230+
.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
231+
BIT(MDP_SSPP_TOP0_INTR2) | \
232+
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
233+
BIT(MDP_INTF0_7xxx_INTR) | \
234+
BIT(MDP_INTF1_7xxx_INTR) | \
235+
BIT(MDP_INTF2_7xxx_INTR) | \
236+
BIT(MDP_INTF3_7xxx_INTR),
231237
};
232238

233239
#endif

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

Lines changed: 0 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -102,79 +102,6 @@
102102

103103
#define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
104104

105-
#define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
106-
BIT(MDP_SSPP_TOP0_INTR2) | \
107-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
108-
BIT(MDP_INTF0_INTR) | \
109-
BIT(MDP_INTF1_INTR) | \
110-
BIT(MDP_INTF2_INTR) | \
111-
BIT(MDP_INTF3_INTR) | \
112-
BIT(MDP_AD4_0_INTR) | \
113-
BIT(MDP_AD4_1_INTR))
114-
115-
#define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
116-
BIT(MDP_SSPP_TOP0_INTR2) | \
117-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
118-
BIT(MDP_INTF0_INTR) | \
119-
BIT(MDP_INTF1_INTR))
120-
121-
#define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
122-
BIT(MDP_SSPP_TOP0_INTR2) | \
123-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
124-
BIT(MDP_INTF0_7xxx_INTR) | \
125-
BIT(MDP_INTF1_7xxx_INTR) | \
126-
BIT(MDP_INTF5_7xxx_INTR))
127-
128-
#define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
129-
BIT(MDP_SSPP_TOP0_INTR2) | \
130-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
131-
BIT(MDP_INTF0_INTR) | \
132-
BIT(MDP_INTF1_INTR) | \
133-
BIT(MDP_INTF2_INTR) | \
134-
BIT(MDP_INTF3_INTR) | \
135-
BIT(MDP_INTF4_INTR))
136-
137-
#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
138-
BIT(MDP_SSPP_TOP0_INTR2) | \
139-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
140-
BIT(MDP_INTF0_7xxx_INTR) | \
141-
BIT(MDP_INTF1_7xxx_INTR) | \
142-
BIT(MDP_INTF2_7xxx_INTR) | \
143-
BIT(MDP_INTF3_7xxx_INTR))
144-
145-
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
146-
BIT(MDP_SSPP_TOP0_INTR2) | \
147-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
148-
BIT(MDP_INTF0_INTR) | \
149-
BIT(MDP_INTF1_INTR) | \
150-
BIT(MDP_INTF2_INTR) | \
151-
BIT(MDP_INTF3_INTR) | \
152-
BIT(MDP_INTF4_INTR) | \
153-
BIT(MDP_INTF5_INTR) | \
154-
BIT(MDP_AD4_0_INTR) | \
155-
BIT(MDP_AD4_1_INTR))
156-
157-
#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
158-
BIT(MDP_SSPP_TOP0_INTR2) | \
159-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
160-
BIT(MDP_INTF0_7xxx_INTR) | \
161-
BIT(MDP_INTF1_7xxx_INTR) | \
162-
BIT(MDP_INTF2_7xxx_INTR) | \
163-
BIT(MDP_INTF3_7xxx_INTR) | \
164-
BIT(MDP_INTF4_7xxx_INTR) | \
165-
BIT(MDP_INTF5_7xxx_INTR) | \
166-
BIT(MDP_INTF6_7xxx_INTR) | \
167-
BIT(MDP_INTF7_7xxx_INTR) | \
168-
BIT(MDP_INTF8_7xxx_INTR))
169-
170-
#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
171-
BIT(MDP_SSPP_TOP0_INTR2) | \
172-
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
173-
BIT(MDP_INTF0_7xxx_INTR) | \
174-
BIT(MDP_INTF1_7xxx_INTR) | \
175-
BIT(MDP_INTF2_7xxx_INTR) | \
176-
BIT(MDP_INTF3_7xxx_INTR))
177-
178105
#define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
179106
BIT(DPU_WB_UBWC) | \
180107
BIT(DPU_WB_YUV_CONFIG) | \

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