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Fix multisynth divider range #19

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Merged
merged 1 commit into from
Mar 31, 2021
Merged

Fix multisynth divider range #19

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4 changes: 2 additions & 2 deletions adafruit_si5351.py
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Original file line number Diff line number Diff line change
Expand Up @@ -306,7 +306,7 @@ def configure_integer(self, pll, divider):
divider. This is the most accurate way to set the clock output
frequency but supports less of a range of values.
"""
assert 3 < divider < 901
assert 3 < divider < 2049
divider = int(divider)
# Make sure the PLL is configured (has a frequency set).
assert pll.frequency is not None
Expand All @@ -331,7 +331,7 @@ def configure_fractional(self, pll, divider, numerator, denominator):
fractional divider with numerator/denominator. Again this is less
accurate but has a wider range of output frequencies.
"""
assert 3 < divider < 901
assert 3 < divider < 2049
assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
assert 0 <= numerator < 0xFFFFF
divider = int(divider)
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