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Update STM DFU mode software implementation. #6961

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Sep 29, 2022
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17 changes: 13 additions & 4 deletions ports/stm/supervisor/port.c
Original file line number Diff line number Diff line change
Expand Up @@ -290,13 +290,22 @@ condition and generating hardware reset or using Go command to execute user code
HAL_RCC_DeInit();
HAL_DeInit();

// disable all interupts
__disable_irq();
// Disable all pending interrupts using NVIC
for (uint8_t i = 0; i < MP_ARRAY_SIZE(NVIC->ICER); ++i) {
NVIC->ICER[i] = 0xFFFFFFFF;
}

// Clear all pending interrupts
for (uint8_t i = 0; i < (sizeof(NVIC->ICPR) / NVIC->ICPR[0]); ++i) {
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I looked at this many times before I spotted the problem.

In CircuitPython, you can use MP_ARRAY_SIZE(arr) (in py/misc.h) to compute the size of the array. Note that if the expression arr is actually a pointer instead, it will NOT be detected as an error. (the implementation is just sizeof(arr) / sizeof(arr[0]), more or less)

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@jepler did the changes. Testing now.

// if it is necessary to ensure an interrupt will not be triggered after disabling it in the NVIC,
// add a DSB instruction and then an ISB instruction. (ARM Cortex™-M Programming Guide to
// Memory Barrier Instructions, 4.6 Disabling Interrupts using NVIC)
__DSB();
__ISB();

// Clear all pending interrupts using NVIC
for (uint8_t i = 0; i < MP_ARRAY_SIZE(NVIC->ICPR); ++i) {
NVIC->ICPR[i] = 0xFFFFFFFF;
}

// information about jump addresses has been taken from STM AN2606.
#if defined(STM32F4)
__set_MSP(*((uint32_t *)0x1FFF0000));
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